From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from Atcsqr.andestech.com (unknown [60.248.187.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3182140DFCD for ; Mon, 30 Mar 2026 10:47:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.187.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774867655; cv=none; b=D6qnAWCF9Zkbt1KToYxrdpnd6/P1NcNTOls4akEkSnFqZMorxt8U6/LCaLQuJHiR2qdPyRP1jVYynRiB/h+dMbiikisnAT0eTj+FhcEcGe1kT146wMeAxe0s+EGNsnxZn/Htkln1NgeLQy2WBqVA5gKbjcocwwsa8XDVSIaa8IU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774867655; c=relaxed/simple; bh=zrHDITLakLIpn0eicQi7YjWpbVQ6gGg7UH0uPpSZxgI=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=aAmd5qJ7fSB67JAjnFfvM/20A1p8S62rN5wT/g8nPD2t7kn981UaYg9EapzomZU2jX+ziYcHp9dAhVTYn7uCZbQp1qpmd+meEvvo/Zpx8VS84qEx8jd/SVJcNxrbHbxsKMEuUPVBKNe7992teV6vQ4oSLrPA6nXAxjE3TMkEZF4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.187.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=permerror header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from Atcsqr.andestech.com (localhost [127.0.0.2] (may be forged)) by Atcsqr.andestech.com with ESMTP id 62UARxgv038088 for ; Mon, 30 Mar 2026 18:27:59 +0800 (+08) (envelope-from minachou@andestech.com) Received: from mail.andestech.com (ATCPCS34.andestech.com [10.0.1.134]) by Atcsqr.andestech.com with ESMTP id 62UARlIT038029; Mon, 30 Mar 2026 18:27:47 +0800 (+08) (envelope-from minachou@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS34.andestech.com (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 30 Mar 2026 18:27:47 +0800 From: Hui Min Mina Chou To: , , , , , , , , , , , , , , , CC: , , , "Hui Min Mina Chou" Subject: [PATCH 0/7] refactor Andes cache driver for generic platform support Date: Mon, 30 Mar 2026 18:27:17 +0800 Message-ID: <20260330102724.1012470-1-minachou@andestech.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: ATCPCS33.andestech.com (10.0.1.100) To ATCPCS34.andestech.com (10.0.1.134) X-DKIM-Results: atcpcs34.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL:Atcsqr.andestech.com 62UARxgv038088 This series refactors the Andes cache driver from an AX45MP-specific implementation to a generic Last Level Cache (LLC) driver that supports a broader range of Andes CPU cores. The main motivation is to decouple the driver from AX45MP-specific naming and assumptions, making it easier to support future Andes platforms without duplicating code. Changes in this series: - Refactor the ax45mp_cache driver into a generic andes_llcache driver, introducing support for multiple Andes CPU cores and updating the compatible strings accordingly - Improve initialization by centralizing cache operations - Improve LLC operation performance by switching to relaxed I/O accessors and eliminating unnecessary fence instructions on I/O memory, leveraging the platform's point-to-point strongly ordered channel guarantee. Also fix hart ID mapping to use cpuid_to_hartid_map() for correct behavior in AMP setups - Centralize cache operations and adopt native WBINVAL support, simplifying the cache flush/invalidate path - Rename DT binding schema from andestech,ax45mp-cache to andestech,llcache and update all compatible strings in the RISC-V DTS files accordingly - Add MAINTAINERS entry for the Andes cache driver Hui Min Mina Chou (7): cache: ax45mp_cache: refactor cache driver for generic Andes platform support cache: andes_llcache: refactor initialization and cache operations cache: andes_llcache: improve performance of LLC operation cache: andes_llcache: centralize cache ops and use native WBINVAL dt-bindings: cache: ax45mp-cache: rename ax45mp-cache to llcache dts: riscv: update cache compatible strings to LLC MAINTAINERS: Add maintainers for Andes cache driver ...ache.yaml => andestech,andes-llcache.yaml} | 20 +- MAINTAINERS | 8 + arch/riscv/Kconfig.errata | 2 +- arch/riscv/boot/dts/andes/qilai.dtsi | 4 +- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 2 +- drivers/cache/Kconfig | 6 +- drivers/cache/Makefile | 2 +- drivers/cache/andes_llcache.c | 215 +++++++++++++++++ drivers/cache/ax45mp_cache.c | 217 ------------------ drivers/soc/renesas/Kconfig | 2 +- include/linux/soc/andes/csr.h | 12 + 11 files changed, 254 insertions(+), 236 deletions(-) rename Documentation/devicetree/bindings/cache/{andestech,ax45mp-cache.yaml => andestech,andes-llcache.yaml} (76%) create mode 100644 drivers/cache/andes_llcache.c delete mode 100644 drivers/cache/ax45mp_cache.c create mode 100644 include/linux/soc/andes/csr.h -- 2.34.1