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Wed, 01 Apr 2026 11:35:34 -0700 (PDT) Received: from hu-kuldsing-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b27497af47sm5717965ad.42.2026.04.01.11.35.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Apr 2026 11:35:34 -0700 (PDT) From: Kuldeep Singh Date: Thu, 02 Apr 2026 00:05:10 +0530 Subject: [PATCH 2/2] arm64: dts: qcom: sm8450: Fix ICE reg size Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260402-ice_dt_reg_fix-v1-2-74e4c2129238@oss.qualcomm.com> References: <20260402-ice_dt_reg_fix-v1-0-74e4c2129238@oss.qualcomm.com> In-Reply-To: <20260402-ice_dt_reg_fix-v1-0-74e4c2129238@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Luca Weiss , Eric Biggers Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kuldeep Singh X-Mailer: b4 0.15.1 X-Authority-Analysis: v=2.4 cv=WMlyn3sR c=1 sm=1 tr=0 ts=69cd6577 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=zOmKeGjK1Y_3dRScO7YA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-GUID: RbSJZzWjI78m0aMsq-d1perzMtN0zxOH X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDAxMDE3NCBTYWx0ZWRfX/JCjivtWwxXI 8+omHe1iGE9Db4G/NK6lompZH8+pHMcrxlWmCI95U3AED8cxx+i+GeMJmJ9AuYOwgj+2S8lAH0+ QIucvMqnaGGS4MVoWT00uUSu0D1SrZEUdRz0r16Lz1VADa9IkDBbdBVrVeFck9ZUfenWSZhq+Iu VcauPPh0ECtyf2qKcGQ4b/HUD3XhhL2LnreiuVCIwLxw2RwysYWILPXJpZl+jOriAo4cF41XfY9 yrNZCF+qarDQkhmn7MHvoh+CHXGh+EjFLanRLGT2jl8/+6t5MBW7ZuWoBbbpzr0TuAesAN+hM4L 8OgWN6pvvAMPbds8kt1MkLRDo7gl+sVVKw7yt4SmErwGfmMimyfBP/62V7MGw7v3iU/08RPLLMQ k5Rmlgdmnbp5oJ9I9Tb6S1O8uUjK41D6TUNRm2KOnLpEY5RN7cBpDxY1JIxPPHMonG/5d+E7MjV /S6TBFo04sxaoVHNN5Q== X-Proofpoint-ORIG-GUID: RbSJZzWjI78m0aMsq-d1perzMtN0zxOH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-01_04,2026-04-01_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 adultscore=0 priorityscore=1501 phishscore=0 suspectscore=0 clxscore=1015 malwarescore=0 lowpriorityscore=0 spamscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604010174 The ICE register region size was originally described incorrectly when the ICE hardware was first introduced. The same value was later carried over unchanged when the ICE node was split out from the UFS node into its own DT entry. Correct the register size to match the hardware specification. Fixes: 276ee34a40c1 ("arm64: dts: qcom: sm8450: add Inline Crypto Engine registers and clock") Signed-off-by: Kuldeep Singh --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 920a2d1c04d0..3984d6f8932d 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -5373,7 +5373,7 @@ ufs_mem_phy: phy@1d87000 { ice: crypto@1d88000 { compatible = "qcom,sm8450-inline-crypto-engine", "qcom,inline-crypto-engine"; - reg = <0 0x01d88000 0 0x8000>; + reg = <0 0x01d88000 0 0x18000>; clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; }; -- 2.34.1