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The EIO GPIO block exposes only bank 0 and bank 1 to multiplexed I/O pins, providing a fixed total of 52 GPIO lines (2 banks × 26 pins). Enforce this hardware constraint by requiring exactly 52 entries in gpio-line-names for the EIO variant. Signed-off-by: Shubhrajyoti Datta --- .../devicetree/bindings/gpio/gpio-zynq.yaml | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml index 5e2496379a3c..b8dd279753a5 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml @@ -16,6 +16,7 @@ properties: - xlnx,zynqmp-gpio-1.0 - xlnx,versal-gpio-1.0 - xlnx,pmc-gpio-1.0 + - xlnx,eio-gpio-1.0 reg: maxItems: 1 @@ -30,7 +31,7 @@ properties: gpio-line-names: description: strings describing the names of each gpio line - minItems: 58 + minItems: 52 maxItems: 174 interrupt-controller: true @@ -89,6 +90,17 @@ allOf: minItems: 116 maxItems: 116 + - if: + properties: + compatible: + enum: + - xlnx,eio-gpio-1.0 + then: + properties: + gpio-line-names: + minItems: 52 + maxItems: 52 + required: - compatible - reg -- 2.34.1