From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from DM5PR21CU001.outbound.protection.outlook.com (mail-centralusazon11011020.outbound.protection.outlook.com [52.101.62.20]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F157430C632 for ; Fri, 3 Apr 2026 05:39:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=fail smtp.client-ip=52.101.62.20 ARC-Seal:i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775194758; cv=fail; b=oPM6e6GQdM8kBeNcdOj59CYw+65OqsDaF0Yf//p2c+KeSgyWgBhR9jM3Pd+wrJlCrSnQUWMu6He0CIeiHIGeX4VmfgnJhs3Pe/06mpMzkktp0cINJUvX8kqH5Rd4Lh//PCrMRU+JTH1KE2hDJWOSSLj3b4lL803gg3M9IUIo7tU= ARC-Message-Signature:i=2; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775194758; c=relaxed/simple; bh=HH0e89hRXT9CaFM5kFbXUi+dUa7NKuFd13dAKQCUazQ=; h=From:To:Cc:Subject:Date:Message-ID:Content-Type:MIME-Version; b=ehdvz69Z02WSyyFgc/kAEyDMUrZw5qI1a2BBywqjGy6p8MrdKz8mOWDP7A883TsnfIW+vOGHji1g5Xvc64siEZpj0mxOEh6O9531WQEmFA5UEQSEGa7s4ztGhUKqfnrjThMCOG/O3KzSUw5b5XHWZl9o3X8ebPLxgOy+1oyLmVQ= ARC-Authentication-Results:i=2; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com; spf=fail smtp.mailfrom=nvidia.com; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b=ELfwc0dd; arc=fail smtp.client-ip=52.101.62.20 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=nvidia.com Authentication-Results: smtp.subspace.kernel.org; spf=fail smtp.mailfrom=nvidia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=Nvidia.com header.i=@Nvidia.com header.b="ELfwc0dd" ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=pgmGD98CJSEXfl40OIjtyfgUys0RYqZozuZzLyoxuDCtk0JA+fZkxl1rHvXydrqoVPwQi3esPAqzJpra9hhnKvaXdjKXj51clGoIB+WGPRGoshhdP25qqDLRzHOf0PnbN29Rj/Zc6qUWAImgTtlXszpCHlFlND0k/s4to8o6AAuApssP0/5M7eUHdSgeaocs+sR1mQhnzuh0Kx7SKW7hiiL9sR5EqRjUyqjjwaUyhCK50kWdzZcUwLUY3fX9R8AdpucPv52x5Oj1DoR21xuwnsQS8ot8bx1qyBUNQ61ercv/pC1I0IKyvq3Lmq9A6hrOnTXMQ3Ib7qjd5g/ZGCeUFg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=sTxV/dUgZ7WLzIT3xAM/BJ65UuF/HuXloU46+RpIhF8=; b=BQLsRwmSpHY1bMnwejvA2bz7giDMiUkRWB8QBwKcC6yHzHW2U0+2j3iHGcIP5HiO4oehCqX2KiLb4U1rqmrV2ldUSORLIicwOM14IBD1Zll6+OMvQN+K5nL2sD8YxXPs79wiUGdRjXFO3spLCwwysyhiMZZ0gXrKr376pZqPxhH3yQ+EwOKMus6pRKx6nWUJQVP4ZnoV6wjj53AaLevrmClHwwK6qpuO3z8G5OXNiF8n/p7aoumJGElUe857FXKFi4ar96nUjhs5AD1VpcQ/Azsr8oNm49iXwGYS3PbAP1+pOdLy2P9Mb0tAfvVgXWPwnUMHX5AbIBPY8QaNkN5U7Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=sTxV/dUgZ7WLzIT3xAM/BJ65UuF/HuXloU46+RpIhF8=; b=ELfwc0ddn7RH49gK4C7zaAGthsH+M4pVXznopuZhfdPZHJgN857fdgV3/t91QnNlqda2JetdaQwazbnyMW5NW5bPcjuwcCrjrd42S2SkJO2+BatE3XdVAvl7DqukkkCaCgigbFrGcMSud+HIr4Opd07HsPyPxGHCEJ/DLUgMlpDzdvkxYC5TuWCCZB0BXPs8+G9WIYP6SsMBQivAxTyOTtaudlqcrgOui63R89lTta+Tj5ltzCIwWR9cNeqRZDnoc65um5VQvw45OoSZhSqYkGmWbd6AgLFRt54xZag9hPTZWxnOoJgXjtdMLeHuyIWnImGeq4Yh/cJ//+XM+MAFPQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from LV8PR12MB9620.namprd12.prod.outlook.com (2603:10b6:408:2a1::19) by PH8PR12MB7110.namprd12.prod.outlook.com (2603:10b6:510:22e::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9769.12; Fri, 3 Apr 2026 05:37:10 +0000 Received: from LV8PR12MB9620.namprd12.prod.outlook.com ([fe80::299d:f5e0:3550:1528]) by LV8PR12MB9620.namprd12.prod.outlook.com ([fe80::299d:f5e0:3550:1528%5]) with mapi id 15.20.9769.017; Fri, 3 Apr 2026 05:37:10 +0000 From: Andrea Righi To: Ingo Molnar , Peter Zijlstra , Juri Lelli , Vincent Guittot Cc: Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , K Prateek Nayak , Christian Loehle , Koba Ko , Felix Abecassis , Balbir Singh , Shrikanth Hegde , linux-kernel@vger.kernel.org Subject: [PATCH v2 0/2] sched/fair: SMT-aware asymmetric CPU capacity Date: Fri, 3 Apr 2026 07:31:04 +0200 Message-ID: <20260403053654.1559142-1-arighi@nvidia.com> X-Mailer: git-send-email 2.53.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: MI0P293CA0002.ITAP293.PROD.OUTLOOK.COM (2603:10a6:290:44::7) To LV8PR12MB9620.namprd12.prod.outlook.com (2603:10b6:408:2a1::19) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: LV8PR12MB9620:EE_|PH8PR12MB7110:EE_ X-MS-Office365-Filtering-Correlation-Id: c10fa791-ef27-4bd2-6084-08de91430d09 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|366016|7416014|56012099003|18002099003; X-Microsoft-Antispam-Message-Info: DfJl7VuZeuxGpNjdNgMq4+msMFeq9qiWnPiQJeGbqyja6WE78fA4jbfhdoOqADkSlmd2y9s4XEwzC9jM6qz5ql7uLJbEiwn9k0I0ut7C9xaXdiJeq0Gucsp1soQKZnHIKexHx1zg3WfqdLTIf4304OKUYgXEkvbeDBFwOXo8xFf1tGbj4jNLmGXR2oc80XW4cv7kkQSdmhjax5dmhImPpAA6sqIXzCdCG6OUWTioVCiWsE13WWo8oU4ODVrCvMdPF/gJKr1rJfi6hQRIPmXrS1osMxqFrKPg6VEXW8/Hw160MRDQGmse5boNsJlfM4/CdyEPm33lxNP7HNiQxDTSBF2TTqeVmvqdJtxKKrd0ueFrk4kSw/9UTlcfBnfpz2ULuJRlZry2/VhYFMHk3agl5gHhRH+e8hVvS8nwpuJN2e87uM43ra+jUtSyw/R7lAI2DluHM6bB1qOBt04/5Jc6o3fYAJiwiUGDntDQLR65udhX7m2IgfRS4nPuU08gm29CZ0cGchXho25zeDOxxdknuaj0awlX+omPmBEB7PeGFtq5FzdUaZVfRtyLbsfEqkkhh1kOgWY64TKmbnWlyipo5SDdQpQ9I0WFv6RFejYMB+AVk6oaPc7n4bv3yj8EJL0GVZ0hBuH1Zsh3jBdc1bX2mtBA6+8VBnD3vMnXG0XCG66ulZ3weMw4pvcqV4u2VDKjMU0M97vFfauVZvY4/JsAVcLmL9j1Jkj1CIxFSQ6qLGk= X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:LV8PR12MB9620.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230040)(1800799024)(376014)(366016)(7416014)(56012099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?FSiDSbemcjN9CTckZovGdTEw7mZoCn4Rb8BlyO6iqmXolT32xsWZIGZlAaqw?= =?us-ascii?Q?sKOuzd2O4uD+zXPi/kwTbnDB5LU0KhMwHDmzuLBvPq6W9J4o9ztmwBKeRJ1N?= =?us-ascii?Q?k5ZgYT0KRwuB7GUFbGB7Blcq1VP9nOVDrf3VVROZGOdRHANa+gIsgpe8tl7w?= =?us-ascii?Q?DsNvIclr5a01m0rGPWmu+GxKPYME8Cw2N/BJK/eyPCvHw4iT2EqIrRLbnTrh?= =?us-ascii?Q?IdRdiALwunxk+Yy5eB+hRHo8qkTAn5CmhUNlN4CKnPynPMj2WBoBjlDAZJTc?= =?us-ascii?Q?ilTOSrcy6q6m9VdXhqkt6e/i74yylA52GG3gA5zrcB9Y9FIR8wFKYAZsjQYC?= =?us-ascii?Q?rZuEwct5hFUvTJ9e1iCYuPo1f582I3foud+/8/D1rMG3fDnnLy6PjcAGZMPV?= =?us-ascii?Q?mKUYCx7uxvk6ZRxbZaQ9dnU9GEI7EqRYXoYXx3dk1Iw/upbq/7OD8AVKoMVN?= =?us-ascii?Q?nNX7owi1N/nppjXwLcuxw+ooRQJ7OzLJkG4DF5xEgtKoa0JXWDB2KWgrtFIl?= =?us-ascii?Q?jAnRHPw5I3XzHk1IjxWym2FWipIjsfnmzBtcZ3pqliWc5cVZc7wfvqW2H81A?= =?us-ascii?Q?UmvhJ7jehpVPKz+wk6lttxAftSNFODR5kV42XvOiiHlennTGjU76QRpFDN1V?= =?us-ascii?Q?8KT4ZI++OerdJw0TyjmXd4q+CnCWVqHr5tvra4QOeFC3kbaLPdLTc5/aypDg?= =?us-ascii?Q?G9m7gdhPKcSIdejnCTeipd5CjFl7MQGTP417e+ba1dmYIzb6dztOBVKaxa1r?= =?us-ascii?Q?5Fgdk2q85E5SwnTAO4OvUI9r8aHdwJSdcUqz2M1Uo1iFGws6f3jPbX2IDzke?= =?us-ascii?Q?MYbdWQmKDQjZYAUsmbDkX661wLNIk2mbhCCaRLgbOWpKGStMh3HgV3rUq8BS?= =?us-ascii?Q?3MvjmtgQRMcnZx7doFSjKZiItqvGlTTPUg/Q1BdS41j/oVIPi1ORZVlY/0n5?= =?us-ascii?Q?L/gj3IvSJ8vimPhH+qQUkLMrHXJrmkqM9dR4zdCrZ8plBL1Jv6XCAMOWmXYr?= =?us-ascii?Q?XfmAotNITLxSAHt3kP2Z/WS9EmcbQARCZ4a1mQPmNcNNnqyIAL8Z1WLKyU94?= =?us-ascii?Q?Up2RgkzHrNRTlto1oKOZboSQzUIuO45OzcBWbyRPlieGBsJ7jWUW9z0ASxci?= =?us-ascii?Q?raLpXy6Wat6WhI8j+tRCW96DHGDySJOCzXAsoIFlw/0kX+q0vIus3gv9TRP+?= =?us-ascii?Q?R+cYA1+MyweDUxLzRS3hdTS6qKVkUr06R8BkzN+BlEarcaw3I3ZgUAz6E/ue?= =?us-ascii?Q?ILAtIVWtR0GguO76xN65+3rruPHMr9+NoxqNt4xKRPEkjB/k6OW2AEuGUIZH?= =?us-ascii?Q?B8yYDwT1IFQrf7tuzvD/h8C+7Ae2jWFUtX0LZ7by5DrDFLULDLwYWNO8glWp?= =?us-ascii?Q?dVo8mJqlHsWkvNOO5/NRVgPGI5JHhEltDbYrAyXQe8NmOpCu/54qqG0/G8g0?= =?us-ascii?Q?yFebjy8bQ0Rs4GNACBApUvEwYAxg1IiDR1eALi9BOTelzwg7cYkbnoN7nQkk?= =?us-ascii?Q?7kNQF335XqwRKAWwb3WSAXl5p3L5WHc5ysSH3nroUYDGZxA5sincZ1FBvf6t?= =?us-ascii?Q?H2Q3RFErJQ8aGEKtWRVVHhfonVcwQru3FU0S6rGIbrf/m5sPGdoA40LU6Yzq?= =?us-ascii?Q?kZMzEl+ffBh/0PCsh9Fh2xLKDYStGExFBWk+TOeMDwWY2jctLriyuFsTAe74?= =?us-ascii?Q?3zpMs/z9g5hJBwtC8wZL486kqWVkqiUsllegOfHgsV254Kv+K2M+TSrb/n8q?= =?us-ascii?Q?zyF3DGRuUg=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: c10fa791-ef27-4bd2-6084-08de91430d09 X-MS-Exchange-CrossTenant-AuthSource: LV8PR12MB9620.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Apr 2026 05:37:10.2479 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: UUlR2owLBihe2B9KloBx2Kex05N2j9ZJz7944BajFoOJWc1nPsWbe72In7NFV25ZswOLYzwGSBVinIVe3IXYMA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7110 This series attempts to improve SD_ASYM_CPUCAPACITY scheduling by introducing SMT awareness. = Problem = Nominal per-logical-CPU capacity can overstate usable compute when an SMT sibling is busy, because the physical core doesn't deliver its full nominal capacity. So, several asym-cpu-capacity paths may pick high capacity idle CPUs that are not actually good destinations. = Solution = This patch set aligns those paths with a simple rule already used elsewhere: when SMT is active, prefer fully idle cores and avoid treating partially idle SMT siblings as full-capacity targets where that would mislead load balance. Patch set summary: - Prefer fully-idle SMT cores in asym-capacity idle selection: in the wakeup fast path, extend select_idle_capacity() / asym_fits_cpu() so idle selection can prefer CPUs on fully idle cores. - Reject misfit pulls onto busy SMT siblings on SD_ASYM_CPUCAPACITY. This patch set has been tested on the new Vera Rubin platform, where SMT is enabled and the firmware exposes small frequency variations (+/-~5%) as differences in CPU capacity, resulting in SD_ASYM_CPUCAPACITY being set. Without these patches, performance can drop by up to ~2x with CPU-intensive workloads, because the SD_ASYM_CPUCAPACITY idle selection policy does not account for busy SMT siblings. Alternative approaches have been evaluated, such as equalizing CPU capacities, either by exposing uniform values via firmware or normalizing them in the kernel by grouping CPUs within a small capacity window (+-5%). However, the SMT-aware SD_ASYM_CPUCAPACITY approach has shown better results so far. Improving this policy also seems worthwhile in general, as future platforms may enable SMT with asymmetric CPU topologies. Performance results on Vera Rubin with SD_ASYM_CPUCAPACITY (mainline) vs SD_ASYM_CPUCAPACITY + SMT: - NVBLAS benchblas (one task / SMT core): +---------------------------------+--------+ | Configuration | gflops | +---------------------------------+--------+ | ASYM (mainline) + SIS_UTIL | 5478 | | ASYM (mainline) + NO_SIS_UTIL | 5491 | | | | | NO ASYM + SIS_UTIL | 8912 | | NO ASYM + NO_SIS_UTIL | 8978 | | | | | ASYM + SMT + SIS_UTIL | 9259 | | ASYM + SMT + NO_SIS_UTIL | 9291 | +---------------------------------+--------+ - DCPerf MediaWiki (all CPUs): +---------------------------------+--------+--------+--------+--------+ | Configuration | rps | p50 | p95 | p99 | +---------------------------------+--------+--------+--------+--------+ | ASYM (mainline) + SIS_UTIL | 7994 | 0.052 | 0.223 | 0.246 | | ASYM (mainline) + NO_SIS_UTIL | 7993 | 0.052 | 0.221 | 0.245 | | | | | | | | NO ASYM + SIS_UTIL | 8113 | 0.067 | 0.184 | 0.225 | | NO ASYM + NO_SIS_UTIL | 8093 | 0.068 | 0.184 | 0.223 | | | | | | | | ASYM + SMT + SIS_UTIL | 8129 | 0.076 | 0.149 | 0.188 | | ASYM + SMT + NO_SIS_UTIL | 8138 | 0.076 | 0.148 | 0.186 | +---------------------------------+--------+--------+--------+--------+ In the MediaWiki case SMT awareness is less impactful (compared to equalizing CPU capacities), because for the majority of the run all CPUs are used, but it still seems to provide some benefits at reducing tail latency. See also: - https://lore.kernel.org/lkml/20260324005509.1134981-1-arighi@nvidia.com - https://lore.kernel.org/lkml/20260318092214.130908-1-arighi@nvidia.com Changes in v2: - Rework SMT awareness logic in select_idle_capacity() (K Prateek Nayak) - Drop EAS and find_new_ilb() changes for now - Link to v1: https://lore.kernel.org/all/20260326151211.1862600-1-arighi@nvidia.com Andrea Righi (2): sched/fair: Prefer fully-idle SMT cores in asym-capacity idle selection sched/fair: Reject misfit pulls onto busy SMT siblings on asym-capacity kernel/sched/fair.c | 44 +++++++++++++++++++++++++++++++++++++++----- 1 file changed, 39 insertions(+), 5 deletions(-)