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Tue, 07 Apr 2026 06:03:19 -0700 (PDT) Received: from hu-krichai-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b2749794e8sm181564885ad.53.2026.04.07.06.03.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Apr 2026 06:03:19 -0700 (PDT) From: Krishna Chaitanya Chundru Subject: [PATCH v4 0/5] PCI: qcom: Add D3cold support Date: Tue, 07 Apr 2026 18:33:07 +0530 Message-Id: <20260407-d3cold-v4-0-bb171f75b465@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-B4-Tracking: v=1; b=H4sIAIsA1WkC/3XM3w6CIBiH4VtxHIeDD1ToqPtoHci/ZFMpKVdz3 nvolp7UCduPfc87oWgHbyM6ZhMa7OijD30a/JAh3dT91WJv0kZAoKAAEhumQ2uwclJKoLIkSqF 0fBus8681dL6k3fj4CMN77Y50+V0SJaEgvomRYoKNEY45oq0Afgox5vdn3erQdXl60FIaYddAq 01D0kIqBiBKTjj7o9muGaWbZklzIwqjKw2lLH7oeZ4/GYnYOx8BAAA= X-Change-ID: 20251229-d3cold-bf99921960bb To: Jingoo Han , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Will Deacon Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, jonathanh@nvidia.com, bjorn.andersson@oss.qualcomm.com, Krishna Chaitanya Chundru X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775566994; l=4316; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=bbZHPBwF0Y3DBIKbxtiScwcSKdeSgmMbid936OxbnBU=; b=qB71aTfgISqqMCT6mCJwX0p5orSaap73x00G+PAaNBw94RsyjSLRYSvbPHid5mkc7BTNk2a1a GsosDzP4BIOArgbVzPjURXPk3AYKV286hmCaS8667ujUbbc2zZlgn5c X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-GUID: tQ026bR3_EO2Hz4sb-vyy4zxB4XpckNg X-Proofpoint-ORIG-GUID: tQ026bR3_EO2Hz4sb-vyy4zxB4XpckNg X-Authority-Analysis: v=2.4 cv=c9abhx9l c=1 sm=1 tr=0 ts=69d5009a cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=Z0v7mYVB04eUNMBhXUoA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA3MDEyMSBTYWx0ZWRfX7j8TADNaJxG1 Qe63PbKE4LQJW6jC3ZCzRgVR+scUk3a9Zau9UDxUUnZPY0Ev8TJYflq4UFgjXgslJBGn1vVoqf4 2RELKszsJjaf6x4Pq0C//Ipqxtifn1tdQA1N/nFrD17DJr7hN2iwks3pBUQUaWdXmKG9+rOIq8h klSfspdII/gajaUtbPtVL8Um+8+0pZnGa4F0eIOJZeK9iw5HJf3tAK2a/e9rKzse1lT63JngSYs 3KRw8aCFU81o6RPUuIMmRIqQfgj1mHUzboAo9uY7GgGfDfOqwHxtup1W5wmubLqQ0C6txS2UGeT 7koOSU8/b7LJEYUHwDG+WHAvRvuYzrQYjqiNkd+q7zpILDzuCGV+5dUyj1+rYG51W+zydNroD5v 5hsxWX/oyAg3LaSiBIF04NV8Y47ugvIaFzMrjgyTYUsKJiQ3WPiqVt/EvjHd47DrUXTPZ4fyZ8L slU39YG3YUHP30ugkJw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-07_02,2026-04-07_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 adultscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 spamscore=0 phishscore=0 malwarescore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604070121 This series adds support for putting Qualcomm PCIe host bridges into D3cold when downstream conditions allow it, and introduces a small common helper to determine D3cold eligibility based on endpoint state. On Qualcomm platforms, PCIe host controllers are currently kept powered even when there are no active endpoints (i.e. all endpoints are already in PCI_D3hot). This prevents the SoC from entering deeper low‑power states such as CXPC. While PCIe D3cold support exists in the PCI core, host controller drivers lack a common mechanism to determine whether it is safe to power off the host bridge without breaking active devices or wakeup functionality. As a result, controllers either avoid entering D3cold or depend on rough, driver‑specific workarounds. This series addresses that gap. 1. Introduces pci_host_common_can_enter_d3cold(), a helper that determines whether a host bridge may enter D3cold based on downstream PCIe endpoint state. The helper permits D3cold only when all *active* endpoints are already in PCI_D3hot, and any wakeup‑enabled endpoint supports PME from D3cold. 2. Updates the Designware PCIe host driver to use this helper in the suspend_noirq() path, replacing the existing heuristic that blocked D3cold whenever L1 ASPM was enabled. 3. Enables D3cold support for Qualcomm PCIe controllers by wiring them into the DesignWare common suspend/resume flow and explicitly powering down controller resources when all endpoints are in D3hot. The immediate outcome of this series is that Qualcomm PCIe host bridges can enter D3cold when all endpoints are in D3hot. This is a necessary but not sufficient step toward unblocking CXPC. With this series applied, CXPC can be achieved on systems with no attached NVMe devices. Support for NVMe‑attached systems requires additional changes in NVMe driver, which are being worked on separately. Tested on: - Qualcomm Lemans EVK, Monaco & sc7280 platforms. Validation steps: - Boot without NVMe attach: * PCIe host enters D3cold during suspend * SoC is able to reach CXPC provided other drivers also remove their votes as part of suspend. Signed-off-by: Krishna Chaitanya Chundru --- Changes in v4: - Added new argument to the API to know if there is any device with wakeup enabled and pme can be generated in D3cold. we need this info to decide to turn off power to device or not. - Couple of nits in commit text (Mani). - Link to v3: https://lore.kernel.org/r/20260311-d3cold-v3-0-4d85dc7c2695@oss.qualcomm.com Changes in v3: - Changed the function name from pci_host_common_can_enter_d3cold() to pci_host_common_d3cold_possible() (Mani). - Couple of nits for commit text, newlines etc(Mani). - Removed -ETIMEDOUT check and added -ENODEV & -EIO(Mani). - Link to v2: https://lore.kernel.org/r/20260217-d3cold-v2-0-89b322864043@oss.qualcomm.com Changes in v2: - Updated the cover letter (Bjorn Andersson) - Add get_ltssm helper function to read LTSSM state from parf. - Allow D3cold if there is no driver enabled for a endpoint. - Added a seperate patch to make phy down in deinit part to avoid power leakage. - Revert icc bw voting if resume fails(Bjorn Andersson). - Link to v1: https://lore.kernel.org/r/20260128-d3cold-v1-0-dd8f3f0ce824@oss.qualcomm.com --- Krishna Chaitanya Chundru (5): PCI: host-common: Add helper to determine host bridge D3cold eligibility PCI: qcom: Add .get_ltssm() helper PCI: qcom: Power down PHY via PARF_PHY_CTRL before disabling rails/clocks PCI: dwc: Use common D3cold eligibility helper in suspend path PCI: qcom: Add D3cold support drivers/pci/controller/dwc/pcie-designware-host.c | 11 +- drivers/pci/controller/dwc/pcie-designware.h | 1 + drivers/pci/controller/dwc/pcie-qcom.c | 194 +++++++++++++++------- drivers/pci/controller/pci-host-common.c | 63 +++++++ drivers/pci/controller/pci-host-common.h | 2 + 5 files changed, 204 insertions(+), 67 deletions(-) --- base-commit: 3aae9383f42f687221c011d7ee87529398e826b3 change-id: 20251229-d3cold-bf99921960bb Best regards, -- Krishna Chaitanya Chundru