From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6221351C0B; Wed, 8 Apr 2026 04:46:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775623596; cv=none; b=JGdCXRG+ofCWZonYfi+F6RqKUtsoKd4N6VJKNC6NHsv0geL2vEty+w4qNEZePtU/1MltCauXz40gaGMu1jjlf4vwVTVIRWUPFU3p6gNDq7J1dPzFqiUTSixu8Oj+zafJofWsIzUJCRb2/fJSwmOPWsrQbYeZajVDuw+rCzusI4E= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775623596; c=relaxed/simple; bh=28Pl+OELVDYrjnKHvpqyk9Nc5veDPYZ4OMPdmZMvW7E=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=e3c4uXNwZv/z/6j369v9k3yThyAC43gfyPYReRlhyqvhvm/5OXtk1rnOXepfNAoxwdaH2+eng8zjMw+9h40GlWPJgFVKa5uAkNVzy/QA5dlQ7bGreBrpbN+E79UY3dFmRLmtkWApVSs5MxU5rGnkIYbAw9Lls5s1fJOMqQ2DK9U= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GNN08Dqy; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GNN08Dqy" Received: by smtp.kernel.org (Postfix) with ESMTPS id 70BEBC19424; Wed, 8 Apr 2026 04:46:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775623596; bh=28Pl+OELVDYrjnKHvpqyk9Nc5veDPYZ4OMPdmZMvW7E=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=GNN08DqyJ11gSxnD3eaQxOYp3CWGQGKpfPNAszmFVzKImsJMTa69z+zbJDChRfm+P /ZgTJThtkkelUh2Ap2pvGpqJFjYO76Ob7MXcxwVJPR2TnqoLysVQXNbXk9eRxBDsNS COwnDJj0ejmVnvyRc3/si1Ra+u3PIg7xeekAGlYEfYj+fPbeGn0aww3aEr+AqkqZBs dn1FKdltjmPDI8NAiiNY7JzfxgiKvJyDhV7ZfwFKCbWG3peYCA9pvOFyIGo2Dr0qk4 90GiK2/F27D6jWbssQt5OzRk35xKWitKaHRk/u3Q/ZOKnYV7qNvrubBth88ktnLK03 TuaaCzzGL1dyQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6838DFD5F75; Wed, 8 Apr 2026 04:46:36 +0000 (UTC) From: Charlie Jenkins via B4 Relay Date: Tue, 07 Apr 2026 21:45:51 -0700 Subject: [PATCH 03/16] riscv: kgdb: Use generated instruction headers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260407-riscv_insn_table-v1-3-54b4736a1e77@gmail.com> References: <20260407-riscv_insn_table-v1-0-54b4736a1e77@gmail.com> In-Reply-To: <20260407-riscv_insn_table-v1-0-54b4736a1e77@gmail.com> To: Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Anup Patel , Atish Patra , Conor Dooley , Paolo Bonzini , Andrew Morton , Shuah Khan Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775623594; l=7745; i=thecharlesjenkins@gmail.com; s=2026030; h=from:subject:message-id; bh=wLizDAcF3npqRdFIpBhaPhxXS6KiGYMhVbuxqiXTwRk=; b=ULkzl8mpC5vn084DwHwkXEygvEG8yVKFDX4RkJnxoCg2v5M1nwXI5/2tKWLCId8vNwihiojjR qy7/I6NRim+AGHMDsTRwrA8Glh20aIIJLuZCJ2UZKbKLgEYdkWmgRCu X-Developer-Key: i=thecharlesjenkins@gmail.com; a=ed25519; pk=vpF2USrG+aB6CTbSt34rzJKsAVe/l+GAXo1IomCMETk= X-Endpoint-Received: by B4 Relay for thecharlesjenkins@gmail.com/2026030 with auth_id=663 X-Original-From: Charlie Jenkins Reply-To: thecharlesjenkins@gmail.com From: Charlie Jenkins Migrate the code that is decoding instructions for the use of kgdb single stepping to use the generated instruction headers instead of the hand-written instruction functions. Signed-off-by: Charlie Jenkins --- I tested this again by comparing the original get_step_address() function with this new version and input all possible 32 bit numbers and checked that the next_addr was the same in every case. This is the code I used: void check_step() { for (unsigned long opcode = 0; opcode < ((1ULL << 32) - 1); opcode++) { unsigned long next_addr, next_addr2; get_step_address(opcode, &next_addr); get_step_address2(opcode, &next_addr2); if (next_addr != next_addr2) { printf("opcode: %lu -> %lu != %lu\n", opcode, next_addr, next_addr2); } } } --- arch/riscv/include/asm/insn.h | 21 +++++++++ arch/riscv/kernel/kgdb.c | 102 ++++++++++++++++-------------------------- 2 files changed, 60 insertions(+), 63 deletions(-) diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h index d0e137f9bcd7..c808e1e15192 100644 --- a/arch/riscv/include/asm/insn.h +++ b/arch/riscv/include/asm/insn.h @@ -514,4 +514,25 @@ static __always_inline bool riscv_insn_is_branch(u32 code) #define RVV_EXTRACT_VL_VS_WIDTH(x) RVFDQ_EXTRACT_FL_FS_WIDTH(x) +static inline unsigned long riscv_insn_reg_get_val(unsigned long *regs, u32 index) +{ + /* register 0 is always 0 and not stored in the register struct */ + return index ? *(regs + index) : 0; +} + +#define riscv_insn_branch(_insn, regs_ptr, _opcode, _pc, _comparison, type) \ + ({ \ + unsigned long _ret; \ + if ((type)riscv_insn_reg_get_val( \ + regs_ptr, \ + riscv_insn_##_insn##_extract_xs1(_opcode)) \ + _comparison(type) riscv_insn_reg_get_val( \ + regs_ptr, \ + riscv_insn_##_insn##_extract_xs2(_opcode))) \ + _ret = riscv_insn_##_insn##_extract_imm(_opcode); \ + else \ + _ret = _pc + 4; \ + _ret; \ + }) + #endif /* _ASM_RISCV_INSN_H */ diff --git a/arch/riscv/kernel/kgdb.c b/arch/riscv/kernel/kgdb.c index 15fec5d1e6de..dd878ba6b47e 100644 --- a/arch/riscv/kernel/kgdb.c +++ b/arch/riscv/kernel/kgdb.c @@ -23,97 +23,73 @@ enum { static unsigned long stepped_address; static unsigned int stepped_opcode; -static int decode_register_index(unsigned long opcode, int offset) -{ - return (opcode >> offset) & 0x1F; -} - -static int decode_register_index_short(unsigned long opcode, int offset) -{ - return ((opcode >> offset) & 0x7) + 8; -} - -/* Calculate the new address for after a step */ static int get_step_address(struct pt_regs *regs, unsigned long *next_addr) { unsigned long pc = regs->epc; unsigned long *regs_ptr = (unsigned long *)regs; - unsigned int rs1_num, rs2_num; + unsigned int rs1_num; int op_code; if (get_kernel_nofault(op_code, (void *)pc)) return -EINVAL; + if ((op_code & __INSN_LENGTH_MASK) != __INSN_LENGTH_GE_32) { - if (riscv_insn_is_c_jalr(op_code) || - riscv_insn_is_c_jr(op_code)) { - rs1_num = decode_register_index(op_code, RVC_C2_RS1_OPOFF); - *next_addr = regs_ptr[rs1_num]; - } else if (riscv_insn_is_c_j(op_code) || - riscv_insn_is_c_jal(op_code)) { - *next_addr = RVC_EXTRACT_JTYPE_IMM(op_code) + pc; + if (riscv_insn_is_c_jalr(op_code)) { + *next_addr = regs_ptr[riscv_insn_c_jalr_extract_xs1(op_code)]; + } else if (riscv_insn_is_c_jr(op_code)) { + *next_addr = regs_ptr[riscv_insn_c_jr_extract_xs1(op_code)]; + } else if (riscv_insn_is_c_j(op_code)) { + *next_addr = riscv_insn_c_j_extract_imm(op_code) + pc; + } else if (riscv_insn_is_c_jal(op_code)) { + *next_addr = riscv_insn_c_jal_extract_imm(op_code) + pc; } else if (riscv_insn_is_c_beqz(op_code)) { - rs1_num = decode_register_index_short(op_code, - RVC_C1_RS1_OPOFF); - if (!rs1_num || regs_ptr[rs1_num] == 0) - *next_addr = RVC_EXTRACT_BTYPE_IMM(op_code) + pc; + rs1_num = riscv_insn_c_beqz_extract_xs1(op_code); + if (regs_ptr[8 + rs1_num] == 0) + *next_addr = riscv_insn_c_beqz_extract_imm(op_code) + pc; else *next_addr = pc + 2; } else if (riscv_insn_is_c_bnez(op_code)) { - rs1_num = - decode_register_index_short(op_code, RVC_C1_RS1_OPOFF); - if (rs1_num && regs_ptr[rs1_num] != 0) - *next_addr = RVC_EXTRACT_BTYPE_IMM(op_code) + pc; + rs1_num = riscv_insn_c_bnez_extract_xs1(op_code); + if (regs_ptr[8 + rs1_num] != 0) + *next_addr = riscv_insn_c_bnez_extract_imm(op_code) + pc; else *next_addr = pc + 2; } else { *next_addr = pc + 2; } } else { - if ((op_code & __INSN_OPCODE_MASK) == __INSN_BRANCH_OPCODE) { - bool result = false; - long imm = RV_EXTRACT_BTYPE_IMM(op_code); - unsigned long rs1_val = 0, rs2_val = 0; - - rs1_num = decode_register_index(op_code, RVG_RS1_OPOFF); - rs2_num = decode_register_index(op_code, RVG_RS2_OPOFF); - if (rs1_num) - rs1_val = regs_ptr[rs1_num]; - if (rs2_num) - rs2_val = regs_ptr[rs2_num]; - - if (riscv_insn_is_beq(op_code)) - result = (rs1_val == rs2_val) ? true : false; - else if (riscv_insn_is_bne(op_code)) - result = (rs1_val != rs2_val) ? true : false; - else if (riscv_insn_is_blt(op_code)) - result = - ((long)rs1_val < - (long)rs2_val) ? true : false; - else if (riscv_insn_is_bge(op_code)) - result = - ((long)rs1_val >= - (long)rs2_val) ? true : false; - else if (riscv_insn_is_bltu(op_code)) - result = (rs1_val < rs2_val) ? true : false; - else if (riscv_insn_is_bgeu(op_code)) - result = (rs1_val >= rs2_val) ? true : false; - if (result) - *next_addr = imm + pc; - else - *next_addr = pc + 4; + if (riscv_insn_is_beq(op_code)) { + *next_addr = riscv_insn_branch(beq, regs_ptr, op_code, + pc, ==, unsigned long); + } else if (riscv_insn_is_bne(op_code)) { + *next_addr = riscv_insn_branch(bne, regs_ptr, op_code, + pc, !=, unsigned long); + } else if (riscv_insn_is_blt(op_code)) { + *next_addr = riscv_insn_branch(blt, regs_ptr, op_code, + pc, <, long); + } else if (riscv_insn_is_bge(op_code)) { + *next_addr = riscv_insn_branch(bge, regs_ptr, op_code, + pc, >=, long); + } else if (riscv_insn_is_bltu(op_code)) { + *next_addr = riscv_insn_branch(bltu, regs_ptr, op_code, + pc, <, unsigned long); + } else if (riscv_insn_is_bgeu(op_code)) { + *next_addr = riscv_insn_branch(bgeu, regs_ptr, op_code, + pc, >=, unsigned long); } else if (riscv_insn_is_jal(op_code)) { - *next_addr = RV_EXTRACT_JTYPE_IMM(op_code) + pc; + *next_addr = riscv_insn_jal_extract_imm(op_code) + pc; } else if (riscv_insn_is_jalr(op_code)) { - rs1_num = decode_register_index(op_code, RVG_RS1_OPOFF); + rs1_num = riscv_insn_jalr_extract_xs1(op_code); if (rs1_num) - *next_addr = ((unsigned long *)regs)[rs1_num]; - *next_addr += RV_EXTRACT_ITYPE_IMM(op_code); + *next_addr = regs_ptr[rs1_num]; + *next_addr += riscv_insn_jalr_extract_imm(op_code); } else if (riscv_insn_is_sret(op_code)) { *next_addr = pc; } else { *next_addr = pc + 4; } } + return 0; } -- 2.52.0