From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 124CB355F2B; Wed, 8 Apr 2026 04:46:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775623597; cv=none; b=BSxIj6UGcNgRs6MpUCjwyf+rWloEKs2wwVCEmNUi/EtwZTX/vq2jFPUi7Ph3JRYpi7CJfPuU3kRiiJwk+FGtoG6sKjJz0Ey3Ll9oxtjdUSF62TnoXx+vyro/5XQeZbsPWnigUzWMIY6pzkYgOs0kvrEBcQDBJYOaoQF0jt1lUrI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775623597; c=relaxed/simple; bh=oUL9asvy+zE2dNrRAwplrqDe/MHJwCo7NgVB5/FNQwQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=IFQ20SNf8ui47ZTWNYmTrHJLiVWlewjd/eDYlvSCl/cYdnJB0ab8Y63nSX/5aNBYwavtlRFRH+K0pTLuvbSqQCujacJt/MtF6mhB3W6d+SSXRdCvcCie/f8w66Z5+k1seSIGUAidtK4jA0gUzrxbyLW885/hFmYk4erb4EBW94M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ATfScWCf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ATfScWCf" Received: by smtp.kernel.org (Postfix) with ESMTPS id E1DD7C19425; Wed, 8 Apr 2026 04:46:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775623597; bh=oUL9asvy+zE2dNrRAwplrqDe/MHJwCo7NgVB5/FNQwQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=ATfScWCfZefHXUaxmesU7O0ved1t35WQwwofWUoyc0MizRGKps5XpEf+GPv9ZpmgE FrRJYtkiALxTnZB29AjMrsseEcXnpIBBuD+3agEsL5KZfzkBpy1WhAPLUIPWslaa/V h6mVcsuaCTpwaQmRnS5dde8xMtC0z9PgIjpfT86sziXq+EhzWons1zb/B50MNPGSOT ZHaJoerqzzeyOHlACK+vi5/CULTx0Eui/Ldv85C9snoiBwRnHm/KnLNkP6qCKZI1QI bZCLCxI/aEr5nCmOyLwlS31/stpmafiwTEMaThYG0MNsXBmkIaGEt/VT2LqYxTI310 acY3cIpTD3zSA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA34FFD5F76; Wed, 8 Apr 2026 04:46:36 +0000 (UTC) From: Charlie Jenkins via B4 Relay Date: Tue, 07 Apr 2026 21:45:55 -0700 Subject: [PATCH 07/16] riscv: kvm: Use generated instruction headers for csr code Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260407-riscv_insn_table-v1-7-54b4736a1e77@gmail.com> References: <20260407-riscv_insn_table-v1-0-54b4736a1e77@gmail.com> In-Reply-To: <20260407-riscv_insn_table-v1-0-54b4736a1e77@gmail.com> To: Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Anup Patel , Atish Patra , Conor Dooley , Paolo Bonzini , Andrew Morton , Shuah Khan Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org, Charlie Jenkins X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1775623594; l=2903; i=thecharlesjenkins@gmail.com; s=2026030; h=from:subject:message-id; bh=zjTRDc41ANyFedf3cbSbk5JAhE4813R8ZlVWeNgHH4k=; b=cFumLVLBW7/FLTqc8/qslS5/l43/knn4JqcHGnwby/U3awqE5WHPDYMVQa4US319I3Fc8+sSE zm0gqE8af27AxhLcN+beDIDk2Pe48rb+bCg8mJDVSRseygG8Qjv0eCI X-Developer-Key: i=thecharlesjenkins@gmail.com; a=ed25519; pk=vpF2USrG+aB6CTbSt34rzJKsAVe/l+GAXo1IomCMETk= X-Endpoint-Received: by B4 Relay for thecharlesjenkins@gmail.com/2026030 with auth_id=663 X-Original-From: Charlie Jenkins Reply-To: thecharlesjenkins@gmail.com From: Charlie Jenkins Migrate the csr parsing code to use the generated instruction headers instead of the hand-written instruction composition functions. Signed-off-by: Charlie Jenkins --- This is a simple transformation that I have again validated through brute force. --- arch/riscv/kvm/vcpu_insn.c | 47 +++++++++++++++++++++++----------------------- 1 file changed, 24 insertions(+), 23 deletions(-) diff --git a/arch/riscv/kvm/vcpu_insn.c b/arch/riscv/kvm/vcpu_insn.c index 4d89b94128ae..62c4510a40af 100644 --- a/arch/riscv/kvm/vcpu_insn.c +++ b/arch/riscv/kvm/vcpu_insn.c @@ -146,43 +146,44 @@ int kvm_riscv_vcpu_csr_return(struct kvm_vcpu *vcpu, struct kvm_run *run) static int csr_insn(struct kvm_vcpu *vcpu, struct kvm_run *run, ulong insn) { + #define GET_REG(_rd) (*((unsigned long *)(&vcpu->arch.guest_context) + _rd)) + int i, rc = KVM_INSN_ILLEGAL_TRAP; - unsigned int csr_num = insn >> SH_RS2; - unsigned int rs1_num = (insn >> SH_RS1) & MASK_RX; - ulong rs1_val = GET_RS1(insn, &vcpu->arch.guest_context); + unsigned int csr_num; const struct csr_func *tcfn, *cfn = NULL; ulong val = 0, wr_mask = 0, new_val = 0; /* Decode the CSR instruction */ - switch (GET_FUNCT3(insn)) { - case GET_FUNCT3(INSN_MATCH_CSRRW): + if (riscv_insn_is_csrrw(insn)) { wr_mask = -1UL; - new_val = rs1_val; - break; - case GET_FUNCT3(INSN_MATCH_CSRRS): - wr_mask = rs1_val; + new_val = GET_REG(riscv_insn_csrrw_extract_xs1(insn)); + csr_num = riscv_insn_csrrw_extract_csr(insn); + } else if (riscv_insn_is_csrrs(insn)) { + wr_mask = GET_REG(riscv_insn_csrrs_extract_xs1(insn)); new_val = -1UL; - break; - case GET_FUNCT3(INSN_MATCH_CSRRC): - wr_mask = rs1_val; + csr_num = riscv_insn_csrrs_extract_csr(insn); + } else if (riscv_insn_is_csrrc(insn)) { + wr_mask = GET_REG(riscv_insn_csrrs_extract_xs1(insn)); new_val = 0; - break; - case GET_FUNCT3(INSN_MATCH_CSRRWI): + csr_num = riscv_insn_csrrc_extract_csr(insn); + } else if (riscv_insn_is_csrrwi(insn)) { wr_mask = -1UL; - new_val = rs1_num; - break; - case GET_FUNCT3(INSN_MATCH_CSRRSI): - wr_mask = rs1_num; + new_val = riscv_insn_csrrwi_extract_imm(insn); + csr_num = riscv_insn_csrrwi_extract_csr(insn); + } else if (riscv_insn_is_csrrsi(insn)) { + wr_mask = riscv_insn_csrrwi_extract_imm(insn); new_val = -1UL; - break; - case GET_FUNCT3(INSN_MATCH_CSRRCI): - wr_mask = rs1_num; + csr_num = riscv_insn_csrrsi_extract_csr(insn); + } else if (riscv_insn_is_csrrci(insn)) { + wr_mask = GET_REG(riscv_insn_csrrwi_extract_imm(insn)); new_val = 0; - break; - default: + csr_num = riscv_insn_csrrwi_extract_csr(insn); + } else { return rc; } + #undef GET_REG + /* Save instruction decode info */ vcpu->arch.csr_decode.insn = insn; vcpu->arch.csr_decode.return_handled = 0; -- 2.52.0