From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA8D2399036 for ; Tue, 7 Apr 2026 08:45:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775551519; cv=none; b=S0jKxdTYzbX4dr2VO245QKajW9KhYFqxbVdCY7EkKxKPCCj92tX4MrQnsyOiceifBda5iEtPoTL59HGt0TRXLFGjev/KPxcZn34YQQPOg5CToGVixn5hx/70UXUPSOYRNtVNSGS241h6fzr3K/dX+ReFmdfDQyepitU0CQWfBAw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775551519; c=relaxed/simple; bh=yLGUecbtjapkvELzDhc1zXwVeCp6T6d0D9dZmI4HsSw=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=WxYC7/0Fo1Asd/IW79aeZp5yZF6mZ6qe5/Mcq65tv24bTxgTNNGiJhpRkSgfwMh4THVxu7kSczGgVWkpBR4t77PzA66iu5fLh6oH1kx/4DBt4nPAUtHxtCHomWVIFqI1VgX97g4vogLE9OEqbS/NbnBXut41Flln8LNwPH7A3A4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=4lF0LJn0; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=V5Owf4+1; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="4lF0LJn0"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="V5Owf4+1" Date: Tue, 7 Apr 2026 10:45:14 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1775551516; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=LEfzsxUfzdUUGylZzTw2wQa+j6mJ97fK5QE1yMShJpo=; b=4lF0LJn0E/D6w3OMdsrD6ZM3ZlTozhhkFeJFjuierm+0D+9MqJea4t8HSRUCoSTOSOuOgm NU4fiC6dvbjMErDsgI02cN2xHEOrokPJvv+IxDvllf/zrKw6ExDX57zf6ESpQbfoxRD17k 79D8/VBkOYVTrteFZXkJEA9zVpl+DeongFt2TKNrROEVCcfd0ImsTLVhjTLhbY6RUGGcHz lSWVChmkKE0i06JFJgA/z7IxkvH87qVWmKm4WVEKHJ3T3mw41Yu2zJSQ2cZfNQ1h5MDDXU ze7bXEiSk1BRGfz0ObjeMUp5YR+ksen1jlD02HWyIuCyMYZepDUNFLV/iBg/UA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1775551516; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=LEfzsxUfzdUUGylZzTw2wQa+j6mJ97fK5QE1yMShJpo=; b=V5Owf4+1QKB3hSAApsCZSLG7ExDYWskhNVU1Wp8CdY/uvtDvTnhtSlBtL1obOOOUFpvk/4 jRsvNOLM51edmTDQ== From: Nam Cao To: Adriano Vero Cc: palmer@dabbelt.com, pjw@kernel.org, aou@eecs.berkeley.edu, alex@ghiti.fr, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] riscv: Add WFI to secondary hart spinwait loop Message-ID: <20260407084514.syOsks4D@linutronix.de> References: <20260407074534.59179-1-litaliano00.contact@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260407074534.59179-1-litaliano00.contact@gmail.com> On Tue, Apr 07, 2026 at 09:45:34AM +0200, Adriano Vero wrote: > The .Lwait_for_cpu_up loop in the RISCV_BOOT_SPINWAIT path busy-polls > __cpu_spinwait_stack_pointer and __cpu_spinwait_task_pointer, burning > power on all non-boot harts while they wait for the primary hart to > complete early boot setup. > > Add a WFI instruction before each polling iteration to allow the > hardware to enter a low-power state while waiting. Per the RISC-V > privileged specification, WFI wakes on any pending interrupt even > with global interrupts disabled (SIE=0), and implementations are > permitted to treat it as a NOP, so this is safe in all contexts. > > The same pattern is already used in .Lsecondary_park in the same > file. > > Signed-off-by: Adriano Vero > --- > arch/riscv/kernel/head.S | 9 ++++++++- > 1 file changed, 8 insertions(+), 1 deletion(-) > > diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S > index 9c99c5ad6..ca208da7c 100644 > --- a/arch/riscv/kernel/head.S > +++ b/arch/riscv/kernel/head.S > @@ -385,7 +385,14 @@ SYM_CODE_START(_start_kernel) > * get far enough along the boot process that it should continue. > */ > .Lwait_for_cpu_up: > - /* FIXME: We should WFI to save some energy here. */ > + /* > + * Wait for the boot hart to populate the stack and task pointers. > + * Use WFI to avoid burning power in a busy-wait loop. Per the > + * RISC-V privileged spec, WFI wakes on a pending interrupt even > + * with global interrupts disabled (e.g. SIE=0), and implementations > + * are permitted to treat it as a NOP, so this is always safe. > + */ > + wfi > REG_L sp, (a1) > REG_L tp, (a2) > beqz sp, .Lwait_for_cpu_up Which interrupt is supposed to wake these CPUs up? Nam