From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B0AE135DA67 for ; Tue, 7 Apr 2026 15:14:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.19 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775574877; cv=none; b=mz8QbvDGRoxcuxg98bZG6dAzId0LlPWV4pV3kUC68WE3q/F1pMR3I63Q0JD4vzEjtCNG6/yN8BPBKedcgMmt84WWvKwlq0HZG4DuF7zLStFw0OgLZurDdAzWxKG3XeWmPpWn4eVl/tc4nyYL8dymV81P5jKonKxR3CulQ0ezcnM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775574877; c=relaxed/simple; bh=rDqzQ6IKyvg1LPwLNOtgEU1ZWw+L1f4L6adY3L4v19s=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=Hs4JpgQSeWMHsFZLkN8du/Zb7PfI+gUHtH4lcXoHlm3VvIPsYqp3glXIbbDVHfASadx9EW9c0jxv9Un+5kzESG2dwX3qi93ghPXBHojQ12jnS1dk5UEkH4Pi0AFk1BI/vVfhq98tsqbXLK9pOme85c/lemCbf2HdeOEDW798l0Q= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=PNPEzzIT; arc=none smtp.client-ip=198.175.65.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="PNPEzzIT" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1775574876; x=1807110876; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=rDqzQ6IKyvg1LPwLNOtgEU1ZWw+L1f4L6adY3L4v19s=; b=PNPEzzITgNoatg3tZX4D1qKE/oYYfYO5FNzRCfG3C5Yp5ksf5gj6Rf2c 4HBQDS8sL8ikgL330mCgsZVzvc8YpsMlwwuvC/1UMGKFzuVpTjABTjfpz MoXfisx0xGCvWuJoF0MryOObBVUssYExZUkRLc6Sx2LR2NIKwCBZd2XiB fr8PKGLJtf6HThG2wNvziAMPsyLadfQX0VXwq04YzIDlMtA7cVah1GJEV XcvyqWD7AfFJd3Yp34pfPv2DMJFA8/AGauc2nNjoHgd2jpgdmQg+/qVmb TcyUxksA9P7dXzKhGbtjoPbvTRwIefKzO1NC3FbKlHnTN60N6UlaVnr0F g==; X-CSE-ConnectionGUID: J9vzDPc6TXSd19phvbbzWA== X-CSE-MsgGUID: M3HYZDSFRAu/5qJB69xabQ== X-IronPort-AV: E=McAfee;i="6800,10657,11752"; a="76439179" X-IronPort-AV: E=Sophos;i="6.23,165,1770624000"; d="scan'208";a="76439179" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by orvoesa111.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Apr 2026 08:14:35 -0700 X-CSE-ConnectionGUID: 4JNd06etR6GCTfSedMvaAQ== X-CSE-MsgGUID: U7ibh3oASVSSS443yexu7Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.23,165,1770624000"; d="scan'208";a="229866728" Received: from black.igk.intel.com ([10.91.253.5]) by fmviesa004.fm.intel.com with ESMTP; 07 Apr 2026 08:14:34 -0700 Received: by black.igk.intel.com (Postfix, from userid 1003) id 3515C98; Tue, 07 Apr 2026 17:14:33 +0200 (CEST) From: Andy Shevchenko To: Andy Shevchenko , linux-kernel@vger.kernel.org Cc: Yury Norov , Rasmus Villemoes Subject: [PATCH v1 1/1] bitops: Update kernel-doc for sign_extendXX() Date: Tue, 7 Apr 2026 17:14:31 +0200 Message-ID: <20260407151431.1793779-1-andriy.shevchenko@linux.intel.com> X-Mailer: git-send-email 2.50.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The sign_extendXX() lack of Return section and have other style issues. Address that by updating kernel-doc accordingly. Signed-off-by: Andy Shevchenko --- include/linux/bitops.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 1fe46703792f..657eab2725ce 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -179,9 +179,11 @@ static inline __u8 ror8(__u8 word, unsigned int shift) /** * sign_extend32 - sign extend a 32-bit value using specified bit as sign-bit * @value: value to sign extend - * @index: 0 based bit index (0<=index<32) to sign bit + * @index: 0 based bit index (0 <= index < 32) to sign bit * * This is safe to use for 16- and 8-bit types as well. + * + * Return: 32-bit sign extended value */ static __always_inline __s32 sign_extend32(__u32 value, int index) { @@ -192,7 +194,11 @@ static __always_inline __s32 sign_extend32(__u32 value, int index) /** * sign_extend64 - sign extend a 64-bit value using specified bit as sign-bit * @value: value to sign extend - * @index: 0 based bit index (0<=index<64) to sign bit + * @index: 0 based bit index (0 <= index < 64) to sign bit + * + * This is safe to use for 32-, 16- and 8-bit types as well. + * + * Return: 64-bit sign extended value */ static __always_inline __s64 sign_extend64(__u64 value, int index) { -- 2.50.1