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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2ca78df8942sm31265060eec.2.2026.04.09.02.12.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Apr 2026 02:12:15 -0700 (PDT) From: Shawn Guo To: Bjorn Andersson Cc: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Deepti Jaggi , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Nikunj Kela , Shazad Hussain , Shawn Guo Subject: [PATCH 8/8] arm64: dts: qcom: sa8255p: Enable sa8255p-ride board support Date: Thu, 9 Apr 2026 17:11:00 +0800 Message-ID: <20260409091100.474358-9-shengchao.guo@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260409091100.474358-1-shengchao.guo@oss.qualcomm.com> References: <20260409091100.474358-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDA5MDA4MSBTYWx0ZWRfX8ZaxuJl8y2DD THK2MwO084RQqX7LHhdo5obdYQAquHOHXcstVcSEdRmOlwTAX2pbO5XyDewpchK7TnNjEw6MHGD +AV7rifrKlNrtgudndz5XG1fAUG8pEhL4Ac68hJkInXPgxVFDT2UfhyW6hiJfoWLDtl+xOo3U+Y ITWuLRwJpTIheQNBREZL+tNRFFE4OLimhJtMnjS46ctpsL5K6UtbCkAYrsgMf/WbR6gUOuDitO6 UKIxdQjvng+97cKBzuhnPUxT1DRP2jl+m5lHhkCfZUFjeT77oYkSXi4X+9mZh3IS9Wi+JA7/SEt cMPehHvonVlzJgcbhxUXNjwghldOUIi58ZtdZh+jGGt0ma36jBCkJ8wKZWfR0nE/qlZLf65qYLt f+MOfAgH6WSWxI5kIvkx0TqI1lJGTyCAJ4PIp6l0MKfAEtRt8AeQyqvyAVq/eg5QvK7nt8yHF6D u8U+tH2kdSAO73eN6WA== X-Authority-Analysis: v=2.4 cv=eKIjSnp1 c=1 sm=1 tr=0 ts=69d76d71 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=MNDMu2h6GyehcEZcpm4A:9 a=PxkB5W3o20Ba91AHUih5:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: J4VuyOjkLjJC53dGWI4xowc6jGhVezWH X-Proofpoint-ORIG-GUID: J4VuyOjkLjJC53dGWI4xowc6jGhVezWH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-09_02,2026-04-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 impostorscore=0 phishscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 spamscore=0 suspectscore=0 malwarescore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604090081 From: Nikunj Kela Add initial device tree support for the SA8255P Ride board. Enable UFS storage, UART10 as the serial console, PCIe EP interfaces, thermal zones for PMM8654AU sensors, and SCMI protocol nodes. Co-developed-by: Shazad Hussain Signed-off-by: Shazad Hussain Signed-off-by: Nikunj Kela Co-developed-by: Deepti Jaggi Signed-off-by: Deepti Jaggi Reviewed-by: Bartosz Golaszewski Signed-off-by: Shawn Guo --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sa8255p-ride.dts | 222 ++++++++++++++++++++++ 2 files changed, 223 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sa8255p-ride.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index d69e5f3132c4..722532f4e82f 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -201,6 +201,7 @@ qrb5165-rb5-vision-mezzanine-dtbs := qrb5165-rb5.dtb qrb5165-rb5-vision-mezzanin dtb-$(CONFIG_ARCH_QCOM) += qrb5165-rb5-vision-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += qru1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8155p-adp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sa8255p-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8295p-adp.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8540p-ride.dtb dtb-$(CONFIG_ARCH_QCOM) += sa8775p-ride.dtb diff --git a/arch/arm64/boot/dts/qcom/sa8255p-ride.dts b/arch/arm64/boot/dts/qcom/sa8255p-ride.dts new file mode 100644 index 000000000000..9b83ccf32664 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sa8255p-ride.dts @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include + +#include "lemans-sa8255p.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SA8255P Ride"; + compatible = "qcom,sa8255p-ride", "qcom,sa8255p"; + + aliases { + serial0 = &uart10; + serial1 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + thermal-zones { + pmm8654au_0_thermal: pm8255-0-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&scmi23_sensor 0>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmm8654au_1_thermal: pm8255-1-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&scmi23_sensor 1>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmm8654au_2_thermal: pm8255-2-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&scmi23_sensor 2>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + pmm8654au_3_thermal: pm8255-3-thermal { + polling-delay-passive = <100>; + thermal-sensors = <&scmi23_sensor 3>; + + trips { + trip0 { + temperature = <105000>; + hysteresis = <0>; + type = "passive"; + }; + + trip1 { + temperature = <125000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; +}; + +&gpll0_board_clk { + clock-frequency = <300000000>; +}; + +&pcie0_ep { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_ep_clkreq_default &pcie0_ep_perst_default + &pcie0_ep_wake_default>; + reset-gpios = <&tlmm 2 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 0 GPIO_ACTIVE_HIGH>; +}; + +&pcie1_ep { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_ep_clkreq_default &pcie1_ep_perst_default + &pcie1_ep_wake_default>; + reset-gpios = <&tlmm 4 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 5 GPIO_ACTIVE_HIGH>; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&scmi3 { + status = "okay"; +}; + +&scmi4 { + status = "okay"; +}; + +&scmi5 { + status = "okay"; +}; + +&scmi6 { + status = "okay"; +}; + +&scmi11 { + status = "okay"; +}; + +&scmi15 { + status = "okay"; +}; + +&scmi23 { + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&uart4 { + status = "okay"; +}; + +&uart10 { + status = "okay"; +}; + +&tlmm { + pcie0_ep_clkreq_default: pcie0-ep-clkreq-default-state { + pins = "gpio1"; + function = "pcie0_clkreq"; + drive-strength = <2>; + bias-disable; + }; + + pcie0_ep_perst_default: pcie0-ep-perst-default-state { + pins = "gpio2"; + function = "gpio"; + drive-strength = <16>; + bias-pull-down; + }; + + pcie0_ep_wake_default: pcie0-ep-wake-default-state { + pins = "gpio0"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + pcie1_ep_clkreq_default: pcie1-ep-clkreq-default-state { + pins = "gpio3"; + function = "pcie1_clkreq"; + drive-strength = <2>; + bias-disable; + }; + + pcie1_ep_perst_default: pcie1-ep-perst-default-state { + pins = "gpio4"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + pcie1_ep_wake_default: pcie1-ep-wake-default-state { + pins = "gpio5"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&ufs_mem_hc { + status = "okay"; +}; + +&xo_board_clk { + clock-frequency = <38400000>; +}; -- 2.43.0