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Fri, 10 Apr 2026 15:53:19 +0800 Received: from RTKEXHMBS05.realtek.com.tw (10.21.1.55) by RTKEXHMBS02.realtek.com.tw (172.21.6.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 10 Apr 2026 15:53:18 +0800 Received: from RTKEXHMBS05.realtek.com.tw (10.21.1.55) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1748.10; Fri, 10 Apr 2026 15:53:18 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS05.realtek.com.tw (10.21.1.55) with Microsoft SMTP Server id 15.2.1748.10 via Frontend Transport; Fri, 10 Apr 2026 15:53:18 +0800 From: Yu-Chun Lin To: CC: , , , , , , , , , , , , , , , , , Subject: Re: [PATCH v6 04/10] clk: realtek: Add support for phase locked loops (PLLs) Date: Fri, 10 Apr 2026 15:53:18 +0800 Message-ID: <20260410075318.2854478-1-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Hi Brian, > Hi Cheng-Yu and Yu-Chun, > > On Thu, Apr 02, 2026 at 03:39:51PM +0800, Yu-Chun Lin wrote: > > From: Cheng-Yu Lee > > > > Provide a full set of PLL operations for programmable PLLs and a read-only > > variant for fixed or hardware-managed PLLs. > > > > Signed-off-by: Cheng-Yu Lee > > Co-developed-by: Yu-Chun Lin > > Signed-off-by: Yu-Chun Lin > > --- > > +static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, > > + unsigned long parent_rate) > > +{ > > + struct clk_pll *clkp = to_clk_pll(hw); > > + const struct freq_table *fv; > > + int ret; > > + > > + fv = ftbl_find_by_rate(clkp->freq_tbl, rate); > > + if (!fv || fv->rate != rate) > > + return -EINVAL; > > + > > + if (clkp->seq_pre_set_freq) { > > + ret = regmap_multi_reg_write(clkp->clkr.regmap, clkp->seq_pre_set_freq, > > + clkp->num_seq_pre_set_freq); > > + if (ret) > > + return ret; > > + } > > + > > + ret = regmap_update_bits(clkp->clkr.regmap, clkp->freq_reg, > > + clkp->freq_mask, fv->val); > > + if (ret) > > + return ret; > > + > > + if (clkp->seq_post_set_freq) { > > + ret = regmap_multi_reg_write(clkp->clkr.regmap, clkp->seq_post_set_freq, > > + clkp->num_seq_post_set_freq); > > + if (ret) > > + return ret; > > + } > > + > > + if (is_power_on(clkp)) { > > + ret = wait_freq_ready(clkp); > > I should have checked Sashiko before I hit send on my last review. > https://sashiko.dev/#/patchset/20260402073957.2742459-1-eleanor.lin%40realtek.com > > It suggested the following: > > In the Common Clock Framework, .set_rate executes under the prepare_lock > mutex, while .enable and .disable execute under the enable_lock spinlock. > > Could an interleaved clk_pll_enable() corrupt the hardware state by running > its seq_power_on sequence concurrently with these multi-step register > updates? > > There also appears to be a potential race condition later in this function: > > if (is_power_on(clkp)) { > ret = wait_freq_ready(clkp); > ... > } > > If .disable() powers off the PLL right before wait_freq_ready() is called, > will wait_freq_ready() poll a disabled PLL and erroneously return > -ETIMEDOUT? Is a private spinlock needed to serialize these operations? > > Brian > Agreed, I will add a private spinlock here. Best Regards, Yu-Chun