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Fri, 10 Apr 2026 11:42:26 -0700 (PDT) Received: from hu-mojha-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82f0c32e744sm4036922b3a.13.2026.04.10.11.42.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Apr 2026 11:42:26 -0700 (PDT) From: Mukesh Ojha To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: cros-qcom-dts-watchers@chromium.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Mukesh Ojha Subject: [PATCH 06/35] irqchip/qcom-pdc: Use FIELD_GET() to extract bank index and bit position Date: Sat, 11 Apr 2026 00:10:43 +0530 Message-ID: <20260410184124.1068210-7-mukesh.ojha@oss.qualcomm.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260410184124.1068210-1-mukesh.ojha@oss.qualcomm.com> References: <20260410184124.1068210-1-mukesh.ojha@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: mhJer5s62DP_kdQ6ygGE6fWc_h8u5twh X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDEwMDE3NCBTYWx0ZWRfX7WBlAsqFLp+D kf+Y00GVAvl6GngknMC//drxuEH0hCEhdZd0sA2kEos4LWogI6P/wLfXbWSLrhFdspr7lf/jpJA imolDSKlSqAkHQvLY4EC6kiYfUpPmqgx2tcEq4L+QFTJGSQ1Teekjs+ZGfSYrp0uxlgJs54uAk4 QvR/rmvD4rurAKQGpPfF6WdY4r4dj2BABzatWpbwlFmAlsxErSRCOH3O5XNwPrgkLB+9SAFZ33p ob1sq7q8fock6gX/gowkDSSKeNhsNr90QPJgEzGin41Of4E8gNLh+0T8U4mfiRcRhsZlsvefOva KfpliL4T/7yR7mHuqLWBWWO1N2NL69kDWQEv1megdVA8WIEsGDuJAhNaU/Pk1i4JJEyO2R++GZs fyPs/INkTIRc/EPaN6ia1ljI8lm1mFLHnQMGCxH+VJZAHwo14+gpky69RLyBhMGTTvcSIGOEozX jolhC36ZMxnWLQKlO8g== X-Proofpoint-GUID: mhJer5s62DP_kdQ6ygGE6fWc_h8u5twh X-Authority-Analysis: v=2.4 cv=VsgTxe2n c=1 sm=1 tr=0 ts=69d94494 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=1nlMVIS8qB_KVi7qAl0A:9 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-10_05,2026-04-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 spamscore=0 suspectscore=0 clxscore=1015 bulkscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604010000 definitions=main-2604100174 The IRQ_ENABLE_BANK register is a bank of 32-bit words where each bit represents one PDC pin. The bank index and bit position within the bank are encoded in the flat pin number as bits [31:5] and [4:0] respectively. Replace the open-coded division and modulo with FIELD_GET() and GENMASK() to make the bit extraction self-documenting and consistent with the FIELD_PREP() style already used in the PDC_VERSION() macro. Signed-off-by: Mukesh Ojha --- drivers/irqchip/qcom-pdc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c index 5e1553334103..638b5d89a141 100644 --- a/drivers/irqchip/qcom-pdc.c +++ b/drivers/irqchip/qcom-pdc.c @@ -110,8 +110,8 @@ static void pdc_enable_intr_bank(int pin_out, bool on) unsigned long enable; u32 index, mask; - index = pin_out / 32; - mask = pin_out % 32; + index = FIELD_GET(GENMASK(31, 5), pin_out); + mask = FIELD_GET(GENMASK(4, 0), pin_out); enable = pdc_reg_read(IRQ_ENABLE_BANK, index); __assign_bit(mask, &enable, on); -- 2.53.0