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Sat, 11 Apr 2026 11:04:21 -0700 (PDT) From: Khalil X-Google-Original-From: Khalil To: broonie@kernel.org, hdegoede@kernel.org, ilpo.jarvinen@linux.intel.com Cc: rf@opensource.cirrus.com, linux-spi@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, Khalil Subject: [PATCH 3/3] spi: pxa2xx: Handle clock gating for GPIO chip select devices Date: Sat, 11 Apr 2026 20:04:14 +0200 Message-ID: <20260411180414.481427-4-khalil@rentman.nl> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260411180414.481427-1-khalil@rentman.nl> References: <20260215135524.1171065-2-khalil@rentman.nl> <20260411180414.481427-1-khalil@rentman.nl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Khalil On Intel LPSS SPI controllers (Cannon Lake and later) with dynamic clock gating (cs_clk_stays_gated=true), the SPI clock is gated when no native chip select is asserted. When using a GPIO chip select (via SPI_CONTROLLER_GPIO_SS), the SPI framework toggles the GPIO and also calls the controller's set_cs callback. Handle this in the pxa2xx cs_assert/cs_deassert functions: when the device uses a GPIO chip select on an LPSS controller, assert native CS in the control register to enable the clock, and force the clock gate on. On deassert, restore both. This is needed on platforms where serial-multi-instantiate installs a GPIO chip select from the peripheral's ACPI GpioIo resource to work around an incomplete cs-gpios property on the SPI controller. Also remove the unconditional num_chipselect bump to 2 that was added as a temporary workaround - the proper fix is now in serial-multi-instantiate. Signed-off-by: Khalil --- drivers/spi/spi-pxa2xx.c | 78 ++++++++++++++++++++------------------- 1 file changed, 41 insertions(+), 37 deletions(-) diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index XXXXXXX..XXXXXXX 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -419,33 +419,43 @@ static void cs_assert(struct spi_device *spi) { struct driver_data *drv_data = spi_controller_get_devdata(spi->controller); - struct gpio_desc *cs_gpio; + const struct lpss_config *config; if (drv_data->ssp_type == CE4100_SSP) { pxa2xx_spi_write(drv_data, SSSR, spi_get_chipselect(spi, 0)); return; } - /* - * For devices with GPIO chip select, toggle the GPIO directly. - * This ensures GPIO CS works on Intel LPSS which only has native CS0. - */ - cs_gpio = spi_get_csgpiod(spi, 0); - if (cs_gpio) { - /* For ACPI: LOW = selected (gpiod_set_value uses logical value) */ - gpiod_set_value_cansleep(cs_gpio, 0); - return; - } - - if (is_lpss_ssp(drv_data)) - lpss_ssp_cs_control(spi, true); + if (is_lpss_ssp(drv_data)) { + config = lpss_get_config(drv_data); + + if (spi_is_csgpiod(spi)) { + /* + * GPIO handles the actual chip select to the device. + * On LPSS controllers with dynamic clock gating, the + * SPI clock won't run unless the native CS state says + * "asserted" in the CS control register. Assert native + * CS in the register to enable the clock, and force + * the clock gate on. + */ + lpss_ssp_cs_control(spi, true); + if (config->cs_clk_stays_gated) { + __lpss_ssp_update_priv(drv_data, + LPSS_PRIV_CLOCK_GATE, + LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK, + LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON); + } + } else { + lpss_ssp_cs_control(spi, true); + } + } } static void cs_deassert(struct spi_device *spi) { struct driver_data *drv_data = spi_controller_get_devdata(spi->controller); - struct gpio_desc *cs_gpio; + const struct lpss_config *config; unsigned long timeout; if (drv_data->ssp_type == CE4100_SSP) @@ -457,19 +467,22 @@ static void cs_deassert(struct spi_device *spi) !time_after(jiffies, timeout)) cpu_relax(); - /* - * For devices with GPIO chip select, toggle the GPIO directly. - * This ensures GPIO CS works on Intel LPSS which only has native CS0. - */ - cs_gpio = spi_get_csgpiod(spi, 0); - if (cs_gpio) { - /* For ACPI: HIGH = deselected (gpiod_set_value uses logical value) */ - gpiod_set_value_cansleep(cs_gpio, 1); - return; - } - - if (is_lpss_ssp(drv_data)) - lpss_ssp_cs_control(spi, false); + if (is_lpss_ssp(drv_data)) { + config = lpss_get_config(drv_data); + + if (spi_is_csgpiod(spi)) { + /* Deassert native CS and restore clock gating */ + lpss_ssp_cs_control(spi, false); + if (config->cs_clk_stays_gated) { + __lpss_ssp_update_priv(drv_data, + LPSS_PRIV_CLOCK_GATE, + LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK, + LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_OFF); + } + } else { + lpss_ssp_cs_control(spi, false); + } + } } static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level) @@ -1454,13 +1467,6 @@ static int pxa2xx_spi_probe(struct device *dev, ...) } } controller->num_chipselect = platform_info->num_chipselect; - - /* Fix for HP EliteBook CS35L56 speakers - need at least 2 chip selects */ - if (is_lpss_ssp(drv_data) && controller->num_chipselect < 2) { - dev_info(dev, "Increasing num_chipselect from %d to 2 for LPSS audio\n", - controller->num_chipselect); - controller->num_chipselect = 2; - } controller->use_gpio_descriptors = true; -- 2.43.0