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Sun, 12 Apr 2026 09:32:18 -0700 (PDT) From: Khalil X-Google-Original-From: Khalil To: broonie@kernel.org, hdegoede@redhat.com, ilpo.jarvinen@linux.intel.com Cc: rf@opensource.cirrus.com, linux-spi@vger.kernel.org, platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org, Khalil , Khalil Subject: [PATCH 3/3] spi: pxa2xx: Handle clock gating for GPIO chip select devices Date: Sun, 12 Apr 2026 18:31:51 +0200 Message-ID: <20260412163151.506282-4-khalil@rentman.nl> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260412163151.506282-1-khalil@rentman.nl> References: <20260215135524.1171065-2-khalil@rentman.nl> <20260412163151.506282-1-khalil@rentman.nl> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit On Intel LPSS SPI controllers (Cannon Lake and later) with dynamic clock gating (cs_clk_stays_gated=true), the SPI clock is gated when no native chip select is asserted. When using a GPIO chip select (via SPI_CONTROLLER_GPIO_SS), the SPI framework toggles the GPIO and also calls the controller's set_cs callback. Handle this in the pxa2xx cs_assert/cs_deassert functions: when the device uses a GPIO chip select on an LPSS controller, assert native CS in the control register to enable the clock, and force the clock gate on. On deassert, restore both. This is needed on platforms where serial-multi-instantiate installs a GPIO chip select from the peripheral's ACPI GpioIo resource to work around an incomplete cs-gpios property on the SPI controller. Signed-off-by: Khalil --- drivers/spi/spi-pxa2xx.c | 45 ++++++++++++++++++++++++++++++++++++---- 1 file changed, 41 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c index 6291d7c2e..fe5762063 100644 --- a/drivers/spi/spi-pxa2xx.c +++ b/drivers/spi/spi-pxa2xx.c @@ -419,20 +419,43 @@ static void cs_assert(struct spi_device *spi) { struct driver_data *drv_data = spi_controller_get_devdata(spi->controller); + const struct lpss_config *config; if (drv_data->ssp_type == CE4100_SSP) { pxa2xx_spi_write(drv_data, SSSR, spi_get_chipselect(spi, 0)); return; } - if (is_lpss_ssp(drv_data)) - lpss_ssp_cs_control(spi, true); + if (is_lpss_ssp(drv_data)) { + config = lpss_get_config(drv_data); + + if (spi_is_csgpiod(spi)) { + /* + * GPIO handles the actual chip select to the device. + * On LPSS controllers with dynamic clock gating, the + * SPI clock won't run unless the native CS state says + * "asserted" in the CS control register. Assert native + * CS in the register to enable the clock, and force + * the clock gate on. + */ + lpss_ssp_cs_control(spi, true); + if (config->cs_clk_stays_gated) { + __lpss_ssp_update_priv(drv_data, + LPSS_PRIV_CLOCK_GATE, + LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK, + LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_ON); + } + } else { + lpss_ssp_cs_control(spi, true); + } + } } static void cs_deassert(struct spi_device *spi) { struct driver_data *drv_data = spi_controller_get_devdata(spi->controller); + const struct lpss_config *config; unsigned long timeout; if (drv_data->ssp_type == CE4100_SSP) @@ -444,8 +467,22 @@ static void cs_deassert(struct spi_device *spi) !time_after(jiffies, timeout)) cpu_relax(); - if (is_lpss_ssp(drv_data)) - lpss_ssp_cs_control(spi, false); + if (is_lpss_ssp(drv_data)) { + config = lpss_get_config(drv_data); + + if (spi_is_csgpiod(spi)) { + /* Deassert native CS and restore clock gating */ + lpss_ssp_cs_control(spi, false); + if (config->cs_clk_stays_gated) { + __lpss_ssp_update_priv(drv_data, + LPSS_PRIV_CLOCK_GATE, + LPSS_PRIV_CLOCK_GATE_CLK_CTL_MASK, + LPSS_PRIV_CLOCK_GATE_CLK_CTL_FORCE_OFF); + } + } else { + lpss_ssp_cs_control(spi, false); + } + } } static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level) -- 2.43.0