From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out30-111.freemail.mail.aliyun.com (out30-111.freemail.mail.aliyun.com [115.124.30.111]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CD2A9364029 for ; Tue, 14 Apr 2026 11:02:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.30.111 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776164544; cv=none; b=i/qwPb0YjdAoJC7omcJHxPf/ZeMmbBEmXsdncUU5Nt/P1XxFQK0MWN41uHi7mKJEEZBf+5WMWwtzOiLdh+7VkiT51CciTWHfVqUFE4unBpUfE8dUilKFHO9vI6nOiGNsmEuJDgYqJp5/Z/unP4dC0uLBcXDHP5AFv1wwbSgLUP0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776164544; c=relaxed/simple; bh=V0gvljcvlAkXKyjaCXYyFK1TSQNGNz4yQzf51HrIbGY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=mTH/jIHd0BHaM5DLQTfTKOFb10BJ1SH7BC6RQshBeARM2RvZJ/F9TKjat/kSvEqcMzl04HOv7pkRwesdDMYgzapm6mTjbMfOpqhGr5+sn/f/X7N2Ebu7XJAqYj09bVu4c4iQTiGrw3EKdD97FyRpj5cOg/6cbWYFDGPs60bwbuw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com; spf=pass smtp.mailfrom=linux.alibaba.com; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b=BZ69NpEv; arc=none smtp.client-ip=115.124.30.111 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.alibaba.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.alibaba.com header.i=@linux.alibaba.com header.b="BZ69NpEv" DKIM-Signature:v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.alibaba.com; s=default; t=1776164539; h=From:To:Subject:Date:Message-Id:MIME-Version; bh=rfB7a0xDWMYyCV9WZVJBD2hFjqsh3+EdQUgOYTQc0+w=; b=BZ69NpEvwEYbdS5QBb0TUCFitfgzLw9VR7a/aomZghCbSl17sOVcUTjeiyv9r7itXvAxHbS4PZqIP+s6xFyO+uAVMGurA7BYseTsA6uIV/6nVttgtyHGPzDwV2CrXqnL0Li6OS0lflvDJrZJ/BCDcVMBxuHmK4a/2eCvPgLWVoY= X-Alimail-AntiSpam:AC=PASS;BC=-1|-1;BR=01201311R111e4;CH=green;DM=||false|;DS=||;FP=0|-1|-1|-1|0|-1|-1|-1;HT=maildocker-contentspam033037033178;MF=fangyu.yu@linux.alibaba.com;NM=1;PH=DS;RN=21;SR=0;TI=SMTPD_---0X11DRT3_1776164537; Received: from localhost.localdomain(mailfrom:fangyu.yu@linux.alibaba.com fp:SMTPD_---0X11DRT3_1776164537 cluster:ay36) by smtp.aliyun-inc.com; Tue, 14 Apr 2026 19:02:18 +0800 From: fangyu.yu@linux.alibaba.com To: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, tjeznach@rivosinc.com, jgg@ziepe.ca, kevin.tian@intel.com, baolu.lu@linux.intel.com, vasant.hegde@amd.com, anup@brainfault.org, nutty.liu@hotmail.com, jgg@nvidia.com Cc: guoren@kernel.org, iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Fangyu Yu Subject: [PATCH v2 1/2] iommu/riscv: Advertise Svpbmt support to generic page table Date: Tue, 14 Apr 2026 19:02:11 +0800 Message-Id: <20260414110212.79526-2-fangyu.yu@linux.alibaba.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20260414110212.79526-1-fangyu.yu@linux.alibaba.com> References: <20260414110212.79526-1-fangyu.yu@linux.alibaba.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Fangyu Yu The RISC-V IOMMU can optionally support Svpbmt page-based memory types in its page table format. When present,the generic page table code can use this capability to encode memory attributes (e.g. MMIO vs normal memory) in PTEs. Signed-off-by: Fangyu Yu Reviewed-by: Jason Gunthorpe Reviewed-by: Anup Patel Reviewed-by: Guo Ren Reviewed-by: Nutty Liu Reviewed-by: Kevin Tian --- drivers/iommu/riscv/iommu.c | 2 ++ include/linux/generic_pt/common.h | 4 ++++ 2 files changed, 6 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index c7d0342aa747..e53883935563 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -1194,6 +1194,8 @@ static struct iommu_domain *riscv_iommu_alloc_paging_domain(struct device *dev) cfg.common.features = BIT(PT_FEAT_SIGN_EXTEND) | BIT(PT_FEAT_FLUSH_RANGE) | BIT(PT_FEAT_RISCV_SVNAPOT_64K); + if (iommu->caps & RISCV_IOMMU_CAPABILITIES_SVPBMT) + cfg.common.features |= BIT(PT_FEAT_RISCV_SVPBMT); domain->riscvpt.iommu.nid = dev_to_node(iommu->dev); domain->domain.ops = &riscv_iommu_paging_domain_ops; diff --git a/include/linux/generic_pt/common.h b/include/linux/generic_pt/common.h index fc5d0b5edadc..2683e5b38998 100644 --- a/include/linux/generic_pt/common.h +++ b/include/linux/generic_pt/common.h @@ -188,6 +188,10 @@ enum { * Support the 64k contiguous page size following the Svnapot extension. */ PT_FEAT_RISCV_SVNAPOT_64K = PT_FEAT_FMT_START, + /* + * Support Svpbmt extension: encode page-based memory type (PBMT) in PTEs. + */ + PT_FEAT_RISCV_SVPBMT, }; -- 2.50.1