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This ensures proper PHY initialization by verifying that the clock lane and all active data lanes have entered the stop state before proceeding with further operations. Signed-off-by: Guoniu Zhou --- drivers/media/platform/synopsys/dw-mipi-csi2rx.c | 38 ++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/media/platform/synopsys/dw-mipi-csi2rx.c b/drivers/media/platform/synopsys/dw-mipi-csi2rx.c index 85a2a95bf080..27e4c1027816 100644 --- a/drivers/media/platform/synopsys/dw-mipi-csi2rx.c +++ b/drivers/media/platform/synopsys/dw-mipi-csi2rx.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -35,6 +36,8 @@ #define DW_REG_EXIST BIT(31) #define DW_REG(x) (DW_REG_EXIST | (x)) +#define DPHY_STOPSTATE_CLK_LANE BIT(16) + #define DPHY_TEST_CTRL0_TEST_CLR BIT(0) #define IPI_VCID_VC(x) FIELD_PREP(GENMASK(1, 0), (x)) @@ -65,6 +68,7 @@ enum dw_mipi_csi2rx_regs_index { DW_MIPI_CSI2RX_PHY_TST_CTRL0, DW_MIPI_CSI2RX_PHY_TST_CTRL1, DW_MIPI_CSI2RX_PHY_SHUTDOWNZ, + DW_MIPI_CSI2RX_PHY_STOPSTATE, DW_MIPI_CSI2RX_IPI_DATATYPE, DW_MIPI_CSI2RX_IPI_MEM_FLUSH, DW_MIPI_CSI2RX_IPI_MODE, @@ -87,6 +91,7 @@ struct dw_mipi_csi2rx_drvdata { void (*dphy_assert_reset)(struct dw_mipi_csi2rx_device *csi2); void (*dphy_deassert_reset)(struct dw_mipi_csi2rx_device *csi2); void (*ipi_enable)(struct dw_mipi_csi2rx_device *csi2); + int (*wait_for_phy_stopstate)(struct dw_mipi_csi2rx_device *csi2); }; struct dw_mipi_csi2rx_format { @@ -139,6 +144,7 @@ static const u32 imx93_regs[DW_MIPI_CSI2RX_MAX] = { [DW_MIPI_CSI2RX_PHY_SHUTDOWNZ] = DW_REG(0x40), [DW_MIPI_CSI2RX_DPHY_RSTZ] = DW_REG(0x44), [DW_MIPI_CSI2RX_PHY_STATE] = DW_REG(0x48), + [DW_MIPI_CSI2RX_PHY_STOPSTATE] = DW_REG(0x4c), [DW_MIPI_CSI2RX_PHY_TST_CTRL0] = DW_REG(0x50), [DW_MIPI_CSI2RX_PHY_TST_CTRL1] = DW_REG(0x54), [DW_MIPI_CSI2RX_IPI_MODE] = DW_REG(0x80), @@ -410,6 +416,12 @@ static int dw_mipi_csi2rx_start(struct dw_mipi_csi2rx_device *csi2) dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_RESETN, 1); + if (csi2->drvdata->wait_for_phy_stopstate) { + ret = csi2->drvdata->wait_for_phy_stopstate(csi2); + if (ret) + return ret; + } + if (csi2->drvdata->ipi_enable) csi2->drvdata->ipi_enable(csi2); @@ -856,11 +868,37 @@ static void imx93_csi2rx_dphy_ipi_enable(struct dw_mipi_csi2rx_device *csi2) dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_IPI_MODE, val); } +static int imx93_csi2rx_wait_for_phy_stopstate(struct dw_mipi_csi2rx_device *csi2) +{ + struct device *dev = csi2->dev; + void __iomem *addr; + u32 stopstate_mask; + u32 val; + int ret; + + if (!dw_mipi_csi2rx_has_reg(csi2, DW_MIPI_CSI2RX_PHY_STOPSTATE)) { + dev_err(dev, "phy_stopstate register not available\n"); + return -ENXIO; + } + + stopstate_mask = DPHY_STOPSTATE_CLK_LANE | GENMASK(csi2->lanes_num - 1, 0); + addr = dw_mipi_csi2rx_get_regaddr(csi2, DW_MIPI_CSI2RX_PHY_STOPSTATE); + + ret = readl_poll_timeout(addr, val, (val & stopstate_mask) != stopstate_mask, + 1000, 2000000); + if (ret) + dev_err(dev, "lanes are not in stop state: %#x, expected %#x\n", + val, stopstate_mask); + + return ret; +} + static const struct dw_mipi_csi2rx_drvdata imx93_drvdata = { .regs = imx93_regs, .dphy_assert_reset = imx93_csi2rx_dphy_assert_reset, .dphy_deassert_reset = imx93_csi2rx_dphy_deassert_reset, .ipi_enable = imx93_csi2rx_dphy_ipi_enable, + .wait_for_phy_stopstate = imx93_csi2rx_wait_for_phy_stopstate, }; static const struct of_device_id dw_mipi_csi2rx_of_match[] = { -- 2.34.1