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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82f6b95f222sm1602774b3a.29.2026.04.15.06.33.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Apr 2026 06:33:24 -0700 (PDT) From: Kathiravan Thirumoorthy Subject: [PATCH 0/5] Add minimal boot support for Qualcomm IPQ9650 SoC Date: Wed, 15 Apr 2026 19:03:15 +0530 Message-Id: <20260415-ipq9650_boot_to_shell-v1-0-b37eb4c3a1d1@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAJuT32kC/0WNXQrCMBAGr1LybCA/TbS9ikjZbDcaaU1togjFu xut6NsOfDuzsERzoMTaamEz3UMK8VJAbiqGJ7gciYe+MFNCWaG14GG6NtaIzsWYuxy7dKJh4NI 0Qm17U+8QWfmdZvLh8fHuDyunmzsT5rfsu5jpeivBvM7+vbZaa8r+ankYR65AIkFtPTayvcu3x UEijnEcQ24rsuTBoQCPIFS5ldXgwGjttekbIeUWnNppdng+X3RBUEH5AAAA X-Change-ID: 20260330-ipq9650_boot_to_shell-159027d548cc To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kathiravan Thirumoorthy X-Mailer: b4 0.15.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1776260000; l=2207; i=kathiravan.thirumoorthy@oss.qualcomm.com; s=20230906; h=from:subject:message-id; bh=j4RQSX4jl5tgcvA7X7wtjdziWOCRMMs7pw/KnDPtK00=; b=fE+pC5Svf7xG9In9cOGtvvMwqNJxK51fGOldCl0LSj5QHf0GHix1jmS2/k1cob8UmYjtmjy8s H+Hl6FXJd9iAVkU+/bMbVs5hXClkf4VbUaKhQzHdbr/2CJCiVNUR9Q+ X-Developer-Key: i=kathiravan.thirumoorthy@oss.qualcomm.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Proofpoint-GUID: _aIOjTC-ygi7si4lHsLXkm6dkMcsyGqB X-Authority-Analysis: v=2.4 cv=eLMjSnp1 c=1 sm=1 tr=0 ts=69df93a6 cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=YURS4O9UCPS1-Wi1IM0A:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDE1MDEyNiBTYWx0ZWRfX25iB/z575eTg 2eYSqOoyRyJ7BctL6Zkd/Qc2trQuWRCzKw4OZoEcJMtpJqo1a3TJ3pXy364aZBQPXZyyNUlTy5Z gMsAWWtwhlTUY9OG8HBAcOEAI4aLuB3MYWJt/Ugc1NdRGRm7f7xnoftx0q3/c/8m9n4sacZEl7X PVF5J231TpCedDIMN8P7N9UDGLWmtwNRZIKLZUhvC3KfPZqMWObtHhXJzJYASoqSbGq/2CgZlbP b9I3w8GM3wKsyXyHQ7s3fKPayPhaBAa9Eoy0ky4jJLdtGbqppG3P6AOzRf6gdQQKylSdQwLyuwb y90/YSW9nlJTGrs74Cj5B8wbQQ8KqZp3w4FkW5tOzjaldGg1RsTVifveUGcmuANqpFFMkG/PUVd ZESuoWj8NGa2UeMLIqgCr7a04aW00dBgQAWrM7hxVc4SUMWFpeK1p6/VZCiXqKOIDIj3T9TwBmT YPEF8mbYg9NYNgTaSUA== X-Proofpoint-ORIG-GUID: _aIOjTC-ygi7si4lHsLXkm6dkMcsyGqB X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-15_01,2026-04-13_04,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 clxscore=1015 bulkscore=0 lowpriorityscore=0 impostorscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 spamscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604070000 definitions=main-2604150126 Qualcomm IPQ9650 is a networking SoC targeted at routers, gateways, and access points. This change adds minimal support required to boot the IPQ9650 RDP488 board. Compared to earlier IPQ SoCs, IPQ9650 features a heterogeneous CPU configuration with four Cortex-A55 cores and one Cortex-A78 core, a 2 MB shared L3 cache, SMMU support, IPCC, five PCIe Gen3 controllers, an integrated CDSP for task offloading, enhanced PPE capabilities, and DDR5 memory support. More information can be found at the product page: https://docs.qualcomm.com/doc/87-96766-1/87-96766-1_REV_AA_Qualcomm_Dragonwing_NPro_A8_Elite_Platform_Product_Brief.pdf Signed-off-by: Kathiravan Thirumoorthy --- Kathiravan Thirumoorthy (5): dt-bindings: clock: add Qualcomm IPQ9650 GCC clk: qcom: add Global Clock controller (GCC) driver for IPQ9650 SoC dt-bindings: qcom: add IPQ9650 boards arm64: dts: qcom: add IPQ9650 SoC and rdp488 board support arm64: defconfig: enable IPQ9650 RDP488 base configs Documentation/devicetree/bindings/arm/qcom.yaml | 5 + .../bindings/clock/qcom,ipq9650-gcc.yaml | 68 + arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq9650-rdp488.dts | 79 + arch/arm64/boot/dts/qcom/ipq9650.dtsi | 366 ++ arch/arm64/configs/defconfig | 2 + drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-ipq9650.c | 3794 ++++++++++++++++++++ include/dt-bindings/clock/qcom,ipq9650-gcc.h | 190 + include/dt-bindings/reset/qcom,ipq9650-gcc.h | 228 ++ 11 files changed, 4742 insertions(+) --- base-commit: e6efabc0afca02efa263aba533f35d90117ab283 change-id: 20260330-ipq9650_boot_to_shell-159027d548cc prerequisite-change-id: 20260326-ipq9650_tlmm-2a1cea46fc91:v1 prerequisite-patch-id: 13d4c96c03378602b50fa7a976e57f97f960b018 prerequisite-patch-id: fcc2de8f1b615b06fe2e509bdcb1ffd719274dc6 Best regards, -- Kathiravan Thirumoorthy