From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id EC9AE3EAC71 for ; Wed, 15 Apr 2026 16:55:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776272138; cv=none; b=A9ENVp68OjWX4K9j5EsWJiEF15YErNxMEVvlCVqFUOBQ8Q9DI2fYG5YoxM+H/x7moN8hl6i9O3h1Nniii0LgrIvlBLtVDb7aPu6UWQA8l1Pqa6Z2/8DD+vTzJ+KVpRTW7azefCi9wKcqE0gvaVP0s/ibbJFlT1Evdu9hgMfUGMs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776272138; c=relaxed/simple; bh=AAkzGqlEubbe7OVQcjjz853wRAcx9P/zHI85x3EhPwA=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=S6w7S7jZUIv0aTuGYQ0Wy6ef0leP/g7JmMEvwvnSUIlTrMAZBsD/eo05veD2Km2uND+7RuzlCgCK+i/Pj0Ttc298uP/Sk1vtfFrZj37uZWizHMhWODQ3pbT7ouUJ3qqGOTQgpp7Bn2u3Yp+P+FQyjtZcuIRz3xxVHmfuazTWGls= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=LZ/ToS7m; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="LZ/ToS7m" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CD279354D; Wed, 15 Apr 2026 09:55:30 -0700 (PDT) Received: from e129823.cambridge.arm.com (e129823.arm.com [10.1.197.6]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A1E4B3F7D8; Wed, 15 Apr 2026 09:55:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1776272136; bh=AAkzGqlEubbe7OVQcjjz853wRAcx9P/zHI85x3EhPwA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LZ/ToS7mG0bd2r27BKCQpk8PUeTPSVaF1jWabP6VmV3WArSWTn1ae0iOSkJVyDjhs sXgsXq0G5SV/JFtdE4edED+cg6DKxPN4VNkSzOP8gt19cc8guOSZzPDJObv2e+uAn3 jE2wiGDEiflKJKJFSHDqRTLKk5c+vwMJPhLHa8TE= From: Yeoreum Yun To: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Cc: suzuki.poulose@arm.com, mike.leach@arm.com, james.clark@linaro.org, alexander.shishkin@linux.intel.com, leo.yan@arm.com, jie.gan@oss.qualcomm.com, Yeoreum Yun Subject: [PATCH v5 02/12] coresight: etm4x: fix underflow for nrseqstate Date: Wed, 15 Apr 2026 17:55:18 +0100 Message-Id: <20260415165528.3369607-3-yeoreum.yun@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260415165528.3369607-1-yeoreum.yun@arm.com> References: <20260415165528.3369607-1-yeoreum.yun@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit TCRSEQEVR is implemented only when TCRIDR5.NUMSEQSTATE is 0b100, in which case n ranges from 0 to 2; otherwise, TCRIDR5.NUMSEQSTATE is 0b000. Therefore, drvdata->nrseqstate should be checked before entering the loop. Link: https://developer.arm.com/documentation/ihi0064/latest/ [0] Signed-off-by: Yeoreum Yun --- .../hwtracing/coresight/coresight-etm4x-core.c | 18 ++++++++++-------- .../coresight/coresight-etm4x-sysfs.c | 2 ++ 2 files changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c index 74b7063d130e..ba5b8b423bd4 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c @@ -544,9 +544,11 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata) etm4x_relaxed_write32(csa, config->vissctlr, TRCVISSCTLR); if (drvdata->nr_pe_cmp) etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR); - for (i = 0; i < drvdata->nrseqstate - 1; i++) - etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); + if (drvdata->nrseqstate) { + for (i = 0; i < drvdata->nrseqstate - 1; i++) + etm4x_relaxed_write32(csa, config->seq_ctrl[i], TRCSEQEVRn(i)); + etm4x_relaxed_write32(csa, config->seq_rst, TRCSEQRSTEVR); etm4x_relaxed_write32(csa, config->seq_state, TRCSEQSTR); } @@ -1927,10 +1929,10 @@ static int __etm4_cpu_save(struct etmv4_drvdata *drvdata) if (drvdata->nr_pe_cmp) state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR); - for (i = 0; i < drvdata->nrseqstate - 1; i++) - state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i)); - if (drvdata->nrseqstate) { + for (i = 0; i < drvdata->nrseqstate - 1; i++) + state->trcseqevr[i] = etm4x_read32(csa, TRCSEQEVRn(i)); + state->trcseqrstevr = etm4x_read32(csa, TRCSEQRSTEVR); state->trcseqstr = etm4x_read32(csa, TRCSEQSTR); } @@ -2058,10 +2060,10 @@ static void __etm4_cpu_restore(struct etmv4_drvdata *drvdata) if (drvdata->nr_pe_cmp) etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR); - for (i = 0; i < drvdata->nrseqstate - 1; i++) - etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); - if (drvdata->nrseqstate) { + for (i = 0; i < drvdata->nrseqstate - 1; i++) + etm4x_relaxed_write32(csa, state->trcseqevr[i], TRCSEQEVRn(i)); + etm4x_relaxed_write32(csa, state->trcseqrstevr, TRCSEQRSTEVR); etm4x_relaxed_write32(csa, state->trcseqstr, TRCSEQSTR); } diff --git a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c index e9eeea6240d5..d866dcfa2a36 100644 --- a/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-etm4x-sysfs.c @@ -1395,6 +1395,8 @@ static ssize_t seq_idx_store(struct device *dev, struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent); struct etmv4_config *config = &drvdata->config; + if (!drvdata->nrseqstate) + return -EINVAL; if (kstrtoul(buf, 16, &val)) return -EINVAL; if (val >= drvdata->nrseqstate - 1) -- LEVI:{C3F47F37-75D8-414A-A8BA-3980EC8A46D7}