From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from canpmsgout12.his.huawei.com (canpmsgout12.his.huawei.com [113.46.200.227]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 06C3C39BFEE for ; Thu, 16 Apr 2026 09:33:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=113.46.200.227 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776332028; cv=none; b=YcrqKnsYP6KBkoIonipd+oeSBD1routnnz9VmXe7l0N5GV1gZUHP2LGuB49SetxxZJkEK0H7wcQslYQpr1eXmcqwA9tAigA0T3FksgK9iydcJ9T6zrwewDU5ZxGgKJOMdb/FPMo2EQv8x5o6pQqKroZYdSabLLMrnyVlk2JxXQc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776332028; c=relaxed/simple; bh=kS+GLoS2WkyI+mwpPppgKRaUwPv9N/VNhfpLDMC4eGA=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=WR18N9kaX2vEDA35umiMmDRTIrJ03Ehp4PBMeVfJkJ3vfq8vmXsGQIxhYZtLJOxSSA7JADbbgRFW09Xuv0T2KzHRM32K3qDStklIgzx+PdA9rPAFLM5s8HOzNjzjkBPdXVoW3IRMwXqiOqXc+7LAVPgmk9adCtvAE7rEu4LsI00= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b=LOTNfhZM; arc=none smtp.client-ip=113.46.200.227 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=huawei.com header.i=@huawei.com header.b="LOTNfhZM" dkim-signature: v=1; a=rsa-sha256; d=huawei.com; s=dkim; c=relaxed/relaxed; q=dns/txt; h=From; bh=vMW8vxgFzwqasxK5Yc+iahhJv6rwiKjWUvfTv57t/YM=; b=LOTNfhZMNENVczJO7o4xC5zTbVKWB4vEyE7PXJsaMOqjhiWr+7XnDAVwcnulbVoIMI3+SNKdP nWNVdYU5PQVcDaLkr7rSazJ/H2aBOfPTCkjreDJ3rMseUNejXfGIc7bQwnhjRq6TeM72MMMuQpi gT2TUKODk8K0ZLokN2CFUnI= Received: from mail.maildlp.com (unknown [172.19.163.163]) by canpmsgout12.his.huawei.com (SkyGuard) with ESMTPS id 4fxCMx1hnXznTVs; Thu, 16 Apr 2026 17:27:25 +0800 (CST) Received: from dggemv706-chm.china.huawei.com (unknown [10.3.19.33]) by mail.maildlp.com (Postfix) with ESMTPS id 9D9E94048B; Thu, 16 Apr 2026 17:33:42 +0800 (CST) Received: from kwepemq100007.china.huawei.com (7.202.195.175) by dggemv706-chm.china.huawei.com (10.3.19.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Thu, 16 Apr 2026 17:33:42 +0800 Received: from localhost.huawei.com (10.169.71.169) by kwepemq100007.china.huawei.com (7.202.195.175) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Thu, 16 Apr 2026 17:33:41 +0800 From: Yongbang Shi To: , , , , , , , , CC: , , , , , , , , Subject: [PATCH for drm-misc-fixes v4 3/4] drm/hisilicon/hibmc: move display contrl config to hibmc_probe() Date: Thu, 16 Apr 2026 17:24:54 +0800 Message-ID: <20260416092455.1990632-4-shiyongbang@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20260416092455.1990632-1-shiyongbang@huawei.com> References: <20260416092455.1990632-1-shiyongbang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: kwepems500001.china.huawei.com (7.221.188.70) To kwepemq100007.china.huawei.com (7.202.195.175) From: Lin He If there's no VGA output, this encoder modeset won't be called, which will cause displaying data from GPU being cut off. It's actually a common display config for DP and VGA, so move the vdac encoder modeset to driver load stage. Fixes: 5294967f4ae4 ("drm/hisilicon/hibmc: Add support for VDAC") Signed-off-by: Lin He Signed-off-by: Yongbang Shi --- ChangeLog: v1 -> v2: - remove tag "Reviewed-by: Tao Tian ", witch will be given in public. - add 'drm-misc-fixes' in subject prefix. --- .../gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c | 14 ++++++++++++ .../gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c | 22 ------------------- 2 files changed, 14 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c index 289304500ab0..c7ce44a5370b 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_drv.c @@ -214,6 +214,18 @@ void hibmc_set_current_gate(struct hibmc_drm_private *priv, unsigned int gate) writel(gate, mmio + gate_reg); } +static void hibmc_display_ctrl(struct hibmc_drm_private *priv) +{ + u32 reg; + + reg = readl(priv->mmio + HIBMC_DISPLAY_CONTROL_HISILE); + reg |= HIBMC_DISPLAY_CONTROL_FPVDDEN(1); + reg |= HIBMC_DISPLAY_CONTROL_PANELDATE(1); + reg |= HIBMC_DISPLAY_CONTROL_FPEN(1); + reg |= HIBMC_DISPLAY_CONTROL_VBIASEN(1); + writel(reg, priv->mmio + HIBMC_DISPLAY_CONTROL_HISILE); +} + static void hibmc_hw_config(struct hibmc_drm_private *priv) { u32 reg; @@ -245,6 +257,8 @@ static void hibmc_hw_config(struct hibmc_drm_private *priv) reg |= HIBMC_MSCCTL_LOCALMEM_RESET(1); writel(reg, priv->mmio + HIBMC_MISC_CTRL); + + hibmc_display_ctrl(priv); } static int hibmc_hw_map(struct hibmc_drm_private *priv) diff --git a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c index 806d54120d89..f5c7857c6586 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c +++ b/drivers/gpu/drm/hisilicon/hibmc/hibmc_drm_vdac.c @@ -86,26 +86,6 @@ static const struct drm_connector_funcs hibmc_connector_funcs = { .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, }; -static void hibmc_encoder_mode_set(struct drm_encoder *encoder, - struct drm_display_mode *mode, - struct drm_display_mode *adj_mode) -{ - u32 reg; - struct drm_device *dev = encoder->dev; - struct hibmc_drm_private *priv = to_hibmc_drm_private(dev); - - reg = readl(priv->mmio + HIBMC_DISPLAY_CONTROL_HISILE); - reg |= HIBMC_DISPLAY_CONTROL_FPVDDEN(1); - reg |= HIBMC_DISPLAY_CONTROL_PANELDATE(1); - reg |= HIBMC_DISPLAY_CONTROL_FPEN(1); - reg |= HIBMC_DISPLAY_CONTROL_VBIASEN(1); - writel(reg, priv->mmio + HIBMC_DISPLAY_CONTROL_HISILE); -} - -static const struct drm_encoder_helper_funcs hibmc_encoder_helper_funcs = { - .mode_set = hibmc_encoder_mode_set, -}; - int hibmc_vdac_init(struct hibmc_drm_private *priv) { struct drm_device *dev = &priv->dev; @@ -128,8 +108,6 @@ int hibmc_vdac_init(struct hibmc_drm_private *priv) goto err; } - drm_encoder_helper_add(encoder, &hibmc_encoder_helper_funcs); - ret = drm_connector_init_with_ddc(dev, connector, &hibmc_connector_funcs, DRM_MODE_CONNECTOR_VGA, -- 2.33.0