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[47.54.130.67]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8b02ae5eaf1sm136505886d6.30.2026.04.22.09.23.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Apr 2026 09:23:52 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1wFaMh-00000008ahB-3LYQ; Wed, 22 Apr 2026 13:23:51 -0300 Date: Wed, 22 Apr 2026 13:23:51 -0300 From: Jason Gunthorpe To: Evangelos Petrongonas Cc: Will Deacon , Robin Murphy , Joerg Roedel , Nicolin Chen , Pranjal Shrivastava , Lu Baolu , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, linux-kernel@vger.kernel.org, nh-open-source@amazon.com, Zeev Zilberman Subject: Re: [PATCH] iommu/arm-smmu-v3: Allow disabling Stage 1 translation Message-ID: <20260422162351.GK3611611@ziepe.ca> References: <20260420123221.20801-1-epetron@amazon.de> <20260420124032.GO2577880@ziepe.ca> <20260422064431.GA49867@dev-dsk-epetron-1c-1d4d9719.eu-west-1.amazon.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20260422064431.GA49867@dev-dsk-epetron-1c-1d4d9719.eu-west-1.amazon.com> On Wed, Apr 22, 2026 at 06:44:31AM +0000, Evangelos Petrongonas wrote: > The motivation is live update of the hypervisor: we want to kexec into a > new kernel while keeping DMA from passthrough devices flowing, which > means the SMMU's translation state has to survive the handover. The Live > Update Orchestrator work [1] and the in-progress  "iommu: Add live > update state preservation" series [2] are building exactly this plumbing > on top of KHO; [2]'s cover letter calls out Arm SMMUv3 support as future > work, and an earlier RFC from Amazon [3] sketched the same idea for > iommufd. It would be appropriate to keep this patch with the rest of that out of tree pile, for example in the series that enables s2 only support in smmuv3. > For this use case, Stage 2 is materially easier to persist than Stage 1, > for structural rather than performance reasons: I don't think so. The driver needs to know each and every STE that will survive KHO. The ones that don't survive need to be reset to abort STEs. From that point it is trivial enough to include the CD memory in the preservation. It would help to send a preparation series to switch the ARM STE and CD logic away from dma_alloc_coherent and use iommu-pages instead, since we only expect iommu-pages to support preservation.. I could maybe see only supporting non-PASID as a first-series, but a CD table with SSID 0 only populated is still pretty trivial. Jason