From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out28-4.mail.aliyun.com (out28-4.mail.aliyun.com [115.124.28.4]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5DBE2BD01B for ; Thu, 23 Apr 2026 06:04:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=115.124.28.4 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776924280; cv=none; b=J/ZQ53yDgnCWq4L9RHr57kzB7dYy88XRV8Cwccb3JOkHWSyCGTQoC9sOzLUKO9cQjYthxRx3Q4GxVPZptpM3arQNsyHlDMWWaOAZdPfIBB2o/8taiIHch0ixxoFG+DlhCjGCw9mv6AoizAhgIlwauqLO75ATmgyR6GmLSa/pO1g= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776924280; c=relaxed/simple; bh=CkXudpdFZ0acAm47EcpuxCNVctJmf53vWkRyvyOn9vQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CT+hoEH/ATEAgmJhheOVS83qCLgUDsXSbOZICzzupagOWYQRbi3MgZxhNhAxqz2ezWbO/zkuoYwNixrs/WGZofus4xUK0KgHXluOmq688rWvZLJkynLAFUAJW0CnqgOHl+oNheocPoWb7k7MKEDVp/vyEUxveP2r/Z95RnjPazY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net; spf=pass smtp.mailfrom=open-hieco.net; arc=none smtp.client-ip=115.124.28.4 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=open-hieco.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=open-hieco.net X-Alimail-AntiSpam:AC=CONTINUE;BC=0.08139738|-1;CH=green;DM=|CONTINUE|false|;DS=CONTINUE|ham_system_inform|0.0236049-0.00466574-0.971729;FP=3018304662273543407|0|0|0|0|-1|-1|-1;HT=maildocker-contentspam011083013073;MF=wanglin@open-hieco.net;NM=1;PH=DS;RN=7;RT=7;SR=0;TI=SMTPD_---.hILPfPY_1776924268; Received: from localhost.localdomain(mailfrom:wanglin@open-hieco.net fp:SMTPD_---.hILPfPY_1776924268 cluster:ay29) by smtp.aliyun-inc.com; Thu, 23 Apr 2026 14:04:29 +0800 From: Lin Wang To: yazen.ghannam@amd.com, mario.limonciello@amd.com, Borislav Petkov Cc: tglx@kernel.org, mingo@redhat.com, x86@kernel.org, linux-kernel@vger.kernel.org Subject: [RFC PATCH v2 3/5] x86/amd_nb: Add amd_nb_set_cache() for external NB cache registration Date: Thu, 23 Apr 2026 14:04:10 +0800 Message-ID: <20260423060420.1785357-4-wanglin@open-hieco.net> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260423060420.1785357-1-wanglin@open-hieco.net> References: <20260423060420.1785357-1-wanglin@open-hieco.net> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Several subsystems (EDAC, MCE decode, ATL) consume the NB cache through node_to_amd_nb() and amd_nb_num(). On Hygon Family 0x18, the AMD enumeration path in amd_cache_northbridges() cannot discover DF nodes because Hygon uses platform-assigned PCI slots rather than the fixed 00:18..1f layout. Hygon therefore needs to populate the NB cache from its own enumeration module (hygon_node.c) without adding Hygon-specific code or includes into amd_nb.c. Add amd_nb_set_cache() as a vendor-neutral data registration interface: the caller builds a struct amd_northbridge[] array, populates the mandatory misc and link device pointers, and transfers ownership to the NB layer. AMD-only legacy features (GART, L3 Index Disable, flags) remain inactive for non-AMD callers because amd_cache_northbridges() -- which sets those features -- is now guarded to AMD-only. This keeps amd_nb.c free of any vendor-specific headers, defines, or branch logic, while allowing non-AMD vendors to satisfy the existing amd_nb consumer contracts. No functional change for AMD systems. Signed-off-by: Lin Wang --- arch/x86/include/asm/amd/nb.h | 7 +++++++ arch/x86/kernel/amd_nb.c | 22 ++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/arch/x86/include/asm/amd/nb.h b/arch/x86/include/asm/amd/nb.h index ddb5108cf46c..0f10911c08d5 100644 --- a/arch/x86/include/asm/amd/nb.h +++ b/arch/x86/include/asm/amd/nb.h @@ -47,6 +47,7 @@ struct amd_northbridge_info { u16 amd_nb_num(void); bool amd_nb_has_feature(unsigned int feature); struct amd_northbridge *node_to_amd_nb(int node); +int amd_nb_set_cache(struct amd_northbridge *nb, u16 num); static inline bool amd_gart_present(void) { @@ -69,6 +70,12 @@ static inline struct amd_northbridge *node_to_amd_nb(int node) { return NULL; } + +static inline int amd_nb_set_cache(struct amd_northbridge *nb, u16 num) +{ + return -ENODEV; +} + #define amd_gart_present(x) false #endif diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index 5d364540673d..8a066cf0f747 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -58,6 +58,25 @@ struct amd_northbridge *node_to_amd_nb(int node) } EXPORT_SYMBOL_GPL(node_to_amd_nb); +/* + * Register a pre-built NB cache from a vendor-specific module (e.g. Hygon). + * Must be called at most once, before any amd_nb consumer is active. + * Returns -EBUSY if the cache is already populated. + */ +int amd_nb_set_cache(struct amd_northbridge *nb, u16 num) +{ + if (!nb || !num) + return -EINVAL; + + if (amd_northbridges.num) + return -EBUSY; + + amd_northbridges.nb = nb; + amd_northbridges.num = num; + return 0; +} +EXPORT_SYMBOL_GPL(amd_nb_set_cache); + static int amd_cache_northbridges(void) { struct amd_northbridge *nb; @@ -66,6 +85,9 @@ static int amd_cache_northbridges(void) if (amd_northbridges.num) return 0; + if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) + return -ENODEV; + amd_northbridges.num = amd_num_nodes(); nb = kzalloc_objs(struct amd_northbridge, amd_northbridges.num); -- 2.43.0