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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by CH2PEPF00000099.mail.protection.outlook.com (10.167.244.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.18 via Frontend Transport; Fri, 24 Apr 2026 09:22:33 +0000 Received: from purico-ed03host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Fri, 24 Apr 2026 04:22:30 -0500 From: Suravee Suthikulpanit To: , CC: , , , , , , Suravee Suthikulpanit Subject: [PATCH v2 1/4] iommu/amd: Drop unused global exclusion range fields and init Date: Fri, 24 Apr 2026 09:22:10 +0000 Message-ID: <20260424092213.16976-2-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260424092213.16976-1-suravee.suthikulpanit@amd.com> References: <20260424092213.16976-1-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PEPF00000099:EE_|MW3PR12MB4442:EE_ X-MS-Office365-Filtering-Correlation-Id: 3300fca7-dd9d-4b57-014d-08dea1e3045f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|1800799024|82310400026|36860700016|18002099003|22082099003|56012099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Kba726Tib4wisN3tfWTzPxraVHJY489H33Od2hg4x6vpZ71beGjIRKWTY8KoCzV6UBjxp3nvSDTl7k3qP5FUHdIP0NVwjmKOwbSBzKSGG3EmoKnhrfuhGwQrLPpLzb/UNqywh3U2cahY9X6E2Hsmh9HdIUIY6ew+dDtYNkB7PKN0sOjIqh1f1gmkEGs/NXxWKogMt/JhqPFNVuat6YrIY4VYuhH6v2fiUITWf8Hqi/32UUpcmBv3mcQk6W1tKqMC1PzNjbwWgtXQFkuhnW4Dq0GZhYcW7RaeNRm3832DuM8AGPKAZfx970CdbLWd84hWTZDJTrNGfA6RS/2KYHXKRG9notrLYy5moKlwoxDOJLlGR9pVW1+h2pvPuLmTwWnqZ6YOto6qSxkcawCpO8C9rnQ6usVXmgu0yQVOv5uRUcv6CHRbF9E7/K4KrwYgk9VW X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 24 Apr 2026 09:22:33.5620 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3300fca7-dd9d-4b57-014d-08dea1e3045f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH2PEPF00000099.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4442 Remove unused struct amd_iommu.exclusion_start/exclusion_length, the MMIO_EXCL_* flag masks, and iommu_set_exclusion_range(). These struct amd_iommu fields were never assigned, so early_enable_iommu() never programmed the hardware exclusion registers through this path. Please note that the exclusion range registers have been repurposed to SNP completion-wait store base / limit registers. So, rename MMIO_EXCL_BASE/LIMIT via to MMIO_COMPL_STORE_BASE/LIMIT instead. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu_types.h | 4 ++-- drivers/iommu/amd/init.c | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index a481d8cbd053..6b0f1b05aa47 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -55,8 +55,8 @@ #define MMIO_CMD_BUF_OFFSET 0x0008 #define MMIO_EVT_BUF_OFFSET 0x0010 #define MMIO_CONTROL_OFFSET 0x0018 -#define MMIO_EXCL_BASE_OFFSET 0x0020 -#define MMIO_EXCL_LIMIT_OFFSET 0x0028 +#define MMIO_COMPL_STORE_BASE_OFFSET 0x0020 +#define MMIO_COMPL_STORE_LIMIT_OFFSET 0x0028 #define MMIO_EXT_FEATURES 0x0030 #define MMIO_PPR_LOG_OFFSET 0x0038 #define MMIO_GA_LOG_BASE_OFFSET 0x00e0 diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c index a33bf3f5ed8a..866249d3673e 100644 --- a/drivers/iommu/amd/init.c +++ b/drivers/iommu/amd/init.c @@ -364,14 +364,14 @@ static void iommu_set_cwwb_range(struct amd_iommu *iommu) * Re-purpose Exclusion base/limit registers for Completion wait * write-back base/limit. */ - memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, + memcpy_toio(iommu->mmio_base + MMIO_COMPL_STORE_BASE_OFFSET, &entry, sizeof(entry)); /* Note: * Default to 4 Kbytes, which can be specified by setting base * address equal to the limit address. */ - memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, + memcpy_toio(iommu->mmio_base + MMIO_COMPL_STORE_LIMIT_OFFSET, &entry, sizeof(entry)); } @@ -991,7 +991,7 @@ static int __init remap_or_alloc_cwwb_sem(struct amd_iommu *iommu) * completion wait buffer (CWB) address. Read and re-use it. */ pr_info_once("Re-using CWB buffers from the previous kernel\n"); - paddr = readq(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET) & PM_ADDR_MASK; + paddr = readq(iommu->mmio_base + MMIO_COMPL_STORE_BASE_OFFSET) & PM_ADDR_MASK; iommu->cmd_sem = iommu_memremap(paddr, PAGE_SIZE); if (!iommu->cmd_sem) return -ENOMEM; -- 2.34.1