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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b5fab208d4sm294960905ad.55.2026.04.26.02.44.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Apr 2026 02:44:58 -0700 (PDT) From: Yingchao Deng Subject: [PATCH v8 0/4] Add Qualcomm extended CTI support Date: Sun, 26 Apr 2026 17:44:37 +0800 Message-Id: <20260426-extended-cti-v8-0-23b900a4902f@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-B4-Tracking: v=1; b=H4sIAIXe7WkC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyLHQUlJIzE vPSU3UzU4B8JSMDIzMDEyMz3dSKktS8lNQU3eSSTF1jozRzI4s0S+PkpEQloJaCotS0zAqwcdG xtbUAjYp5RF4AAAA= To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_yingdeng@quicinc.com, Jinlong Mao , Tingwei Zhang , Jie Gan , Yingchao Deng X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1777196695; l=4590; i=yingchao.deng@oss.qualcomm.com; s=20260426; h=from:subject:message-id; bh=LN6QvXIfvlOgF3WeZb3Zw7L625TymMXRS8Ovh3/G4F4=; b=U/EqHGBz5VvyOajPDJxSXuOSybQ5pe4QqkMyjVAKzteU1fjyXJHIcOZNVEe4TWj0oOBWKIGIZ YAQhD4VLlDUCqKtlzEchAPPnwMAF8SGAzQqh0AGKsP48BPyRIsEE88m X-Developer-Key: i=yingchao.deng@oss.qualcomm.com; a=ed25519; pk=aufKZC4I8k2lqi+B/z87rB5kPPybOn8C3mLosbtw+no= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI2MDEwMyBTYWx0ZWRfX/Ba5KXlcMfcI LLy2oRGCS+Xskdpx9yl8cuQBxS+bajeFAa7F01UyJK0+zYkxJJmB+LEzZBK5wL/qNEFcpyBOLzZ 49BfwPkmt0TL3hzXLAG1W69QIVjxILLPtlEPs2J5mjv+FEqXTU3s2U1GEzL20h99LIowMcNn/oZ aJCLB211aiFNKeU/OlBVH20BZcd253x6f/2AjlhyGJzdXIR65v9NAn+MhLsrleh/sFe0A7kvlFR tEyBbF0iKry3McVxJWMGMq1opRQbYPSnd/V+kL/SwSaM7WxqGfFrE8hhi+jGtrIz/sVeeLuDCpw CAi0ywtD317d3Zpg44Z1pokLicftDXQvsv8Xb7gDu8p2qS3/FRrgirBHmUCaESIqoer3TSWfbLP y0mo0IJPbItn0mtbNxBgJlQ+xso9qmY56DvJqD/I+8CEYorDTcSoWHO+tMIUQL0ZKi6P24dsygl +xjTWPlEOs6m/Wi/gAQ== X-Authority-Analysis: v=2.4 cv=N5IZ0W9B c=1 sm=1 tr=0 ts=69edde9c cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=VwQbUJbxAAAA:8 a=KKAkSRfTAAAA:8 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=ivfPcWm90DfOTC_Zvf4A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 a=cvBusfyB2V15izCimMoJ:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: f1nyaAVTF0SMJUwGMZIJSeCqtdMfa4TP X-Proofpoint-GUID: f1nyaAVTF0SMJUwGMZIJSeCqtdMfa4TP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-26_03,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 lowpriorityscore=0 adultscore=0 phishscore=0 impostorscore=0 malwarescore=0 clxscore=1015 suspectscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604260103 The Qualcomm extended CTI is a heavily parameterized version of ARM’s CSCTI. It allows a debugger to send to trigger events to a processor or to send a trigger event to one or more processors when a trigger event occurs on another processor on the same SoC, or even between SoCs. Qualcomm extended CTI supports up to 128 triggers. And some of the register offsets are changed. The commands to configure CTI triggers are the same as ARM's CTI. Prerequisites: This series depends on the following CoreSight fix: [PATCH v2 1/1] coresight: fix issue where coresight component has no claimtags Link: https://lore.kernel.org/all/20251027223545.2801-2-mike.leach@linaro.org/ Changes in v8: 1. Rebased on top of linux-next-20260424. 2. patch 1: Use devm_bitmap_zalloc() with nr_trig_max instead of per-connection signal counts; add bitmap_zalloc() for filter trigger group. 3. patch 2: Add #include ; move CTIINOUTEN_MAX expansion to patch3. 4. patch 3: wrap CLAIMSET clear with CS_UNLOCK/CS_LOCK; move CTIINOUTEN_MAX to 128 here with comment; fix macro alignment in qcom-cti.h. 5. patch 4: Make qcom_suffix_registers[] static. Changes in v7: 1. Split the extended CTI support into smaller, logically independent patches to improve reviewability. 2. Removed the dual offset-array based register access used in v6 for standard and Qualcomm CTIs. Register addressing is now unified through a single code path by encoding the register index together with the base offset and applying variant-specific translation at the final MMIO access point. 3. Removed ext_reg_sel, extend the CTI sysfs interface to expose banked register instances on Qualcomm CTIs only. Numbered sysfs nodes are hidden on standard ARM CTIs, and on Qualcomm CTIs their visibility is derived from nr_trig_max (32 triggers per bank), ensuring that only registers backed by hardware are exposed. Link to v6 - https://lore.kernel.org/all/20251202-extended_cti-v6-0-ab68bb15c4f5@oss.qualcomm.com/ Changes in v6: 1. Rename regs_idx to ext_reg_sel and add information in documentation file. 2. Reset CLAIMSET to zero for qcom-cti during probe. 3. Retrieve idx value under spinlock. 4. Use yearless copyright for qcom-cti.h. Link to v5 - https://lore.kernel.org/all/20251020-extended_cti-v5-0-6f193da2d467@oss.qualcomm.com/ Changes in v5: 1. Move common part in qcom-cti.h to coresight-cti.h. 2. Convert trigger usage fields to dynamic bitmaps and arrays. 3. Fix holes in struct cti_config to save some space. 4. Revert the previous changes related to the claim tag in cti_enable/disable_hw. Link to v4 - https://lore.kernel.org/linux-arm-msm/20250902-extended_cti-v4-1-7677de04b416@oss.qualcomm.com/ Changes in v4: 1. Read the DEVARCH registers to identify Qualcomm CTI. 2. Add a reg_idx node, and refactor the coresight_cti_reg_show() and coresight_cti_reg_store() functions accordingly. 3. The register offsets specific to Qualcomm CTI are moved to qcom_cti.h. Link to v3 - https://lore.kernel.org/linux-arm-msm/20250722081405.2947294-1-quic_jinlmao@quicinc.com/ Changes in v3: 1. Rename is_extended_cti() to of_is_extended_cti(). 2. Add the missing 'i' when write the CTI trigger registers. 3. Convert the multi-line output in sysfs to single line. 4. Initialize offset arrays using designated initializer. Link to V2 - https://lore.kernel.org/all/20250429071841.1158315-3-quic_jinlmao@quicinc.com/ Changes in V2: 1. Add enum for compatible items. 2. Move offset arrays to coresight-cti-core Signed-off-by: Yingchao Deng --- Yingchao Deng (4): coresight: cti: Convert trigger usage fields to dynamic bitmaps and arrays coresight: cti: encode trigger register index in register offsets coresight: cti: add Qualcomm extended CTI identification and quirks coresight: cti: expose banked sysfs registers for Qualcomm extended CTI drivers/hwtracing/coresight/coresight-cti-core.c | 118 ++++++++++++++++----- .../hwtracing/coresight/coresight-cti-platform.c | 26 +++-- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 76 +++++++++++-- drivers/hwtracing/coresight/coresight-cti.h | 32 ++++-- drivers/hwtracing/coresight/qcom-cti.h | 65 ++++++++++++ 5 files changed, 265 insertions(+), 52 deletions(-) --- base-commit: 8594d92c94a3624acf07acf634a5e73a8c8f63e2 change-id: 20260426-extended-cti-32f728f93cba Best regards, -- Yingchao Deng