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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2b5fab208d4sm294960905ad.55.2026.04.26.02.45.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Apr 2026 02:45:15 -0700 (PDT) From: Yingchao Deng Date: Sun, 26 Apr 2026 17:44:41 +0800 Subject: [PATCH v8 4/4] coresight: cti: expose banked sysfs registers for Qualcomm extended CTI Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260426-extended-cti-v8-4-23b900a4902f@oss.qualcomm.com> References: <20260426-extended-cti-v8-0-23b900a4902f@oss.qualcomm.com> In-Reply-To: <20260426-extended-cti-v8-0-23b900a4902f@oss.qualcomm.com> To: Suzuki K Poulose , Mike Leach , James Clark , Leo Yan , Alexander Shishkin Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, quic_yingdeng@quicinc.com, Jinlong Mao , Tingwei Zhang , Jie Gan , Yingchao Deng X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1777196695; l=4661; i=yingchao.deng@oss.qualcomm.com; s=20260426; h=from:subject:message-id; bh=OLSSErJr7xMEKOb+hZ/LbjI+CM4RcZpu2NN74Ss6L14=; b=rIBj4R3Di+1yR8dNdgF+nHpt5UGIVdG09pNVsdxHQm/RGUTcM0OuFsgMKvZA1tO2yFe0EVzWQ Jj75zoM14SzAWrvwKEdYSs3i2cWj0S7Yv0miEAYqQKslPdcqt9lS0Sr X-Developer-Key: i=yingchao.deng@oss.qualcomm.com; a=ed25519; pk=aufKZC4I8k2lqi+B/z87rB5kPPybOn8C3mLosbtw+no= X-Proofpoint-GUID: sqT2alWo4nllfj_IgazEmKHhnuBAVGP- X-Proofpoint-ORIG-GUID: sqT2alWo4nllfj_IgazEmKHhnuBAVGP- X-Authority-Analysis: v=2.4 cv=Y+fIdBeN c=1 sm=1 tr=0 ts=69eddead cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=2umZ0bgHSShhNh9j1XYA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI2MDEwMiBTYWx0ZWRfXz1lS0qsCVpX6 UgxlQKpX1WFXL0GJQKYkFqQLrmOVPmhyv41HBRCrS5t0yDgHFFf6VQiYS6vE1OLH2aLj8Hn/FAu KXthryWFPDU/oLuyZjM519nFgwlHiKW+exJ6OiedNjRmhXs8sX1E3hZcv1UgAqVLTR5tHbpFx+E 8dMJDmnqpOx/vnuVwoqQLzLkq8z3ymGhh+Cl+vQgz2YRpn6MSKHweEapxAcKPKMCnRk40z5mHss QWQeiZPhN8Ws/tdLAAWZxKLsWfQTU7efLwJZA4TOm9rhiUind0ub6bEdk1Xz7p8qSkgMFP688vv GJph5k8SBk86QTPuVdT/773myYrp6ihAWrTGX4e6qS2DxsAn2tqAUq5onM57PAU0/M9EivSM0sA 5Nr89TsLdJBkuZoh9rKAmBH1VX0CLrxwT+HI1ikPToOVlcPumZT7NrkglbtrNtweiihpx7nwenQ M/O+QjCdw076VADtO/g== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-26_03,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 suspectscore=0 phishscore=0 adultscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604260102 Qualcomm extended CTI implements banked trigger status and integration registers, where each bank covers 32 triggers. Multiple instances of these registers are required to expose the full trigger space. Add static sysfs entries for the banked CTI registers and control their visibility based on the underlying hardware configuration. Numbered sysfs nodes are hidden on standard ARM CTIs, preserving the existing ABI. On Qualcomm CTIs, only banked registers backed by hardware are exposed, with the number of visible banks derived from nr_trig_max. This ensures that userspace only sees registers that are actually implemented, while maintaining compatibility with existing CTI tooling. Signed-off-by: Yingchao Deng --- drivers/hwtracing/coresight/coresight-cti-sysfs.c | 58 +++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/drivers/hwtracing/coresight/coresight-cti-sysfs.c b/drivers/hwtracing/coresight/coresight-cti-sysfs.c index 8b70e7e38ea3..046757e4e9b6 100644 --- a/drivers/hwtracing/coresight/coresight-cti-sysfs.c +++ b/drivers/hwtracing/coresight/coresight-cti-sysfs.c @@ -512,18 +512,36 @@ static struct attribute *coresight_cti_regs_attrs[] = { &dev_attr_appclear.attr, &dev_attr_apppulse.attr, coresight_cti_reg(triginstatus, CTITRIGINSTATUS), + coresight_cti_reg(triginstatus1, CTI_REG_SET_NR_CONST(CTITRIGINSTATUS, 1)), + coresight_cti_reg(triginstatus2, CTI_REG_SET_NR_CONST(CTITRIGINSTATUS, 2)), + coresight_cti_reg(triginstatus3, CTI_REG_SET_NR_CONST(CTITRIGINSTATUS, 3)), coresight_cti_reg(trigoutstatus, CTITRIGOUTSTATUS), + coresight_cti_reg(trigoutstatus1, CTI_REG_SET_NR_CONST(CTITRIGOUTSTATUS, 1)), + coresight_cti_reg(trigoutstatus2, CTI_REG_SET_NR_CONST(CTITRIGOUTSTATUS, 2)), + coresight_cti_reg(trigoutstatus3, CTI_REG_SET_NR_CONST(CTITRIGOUTSTATUS, 3)), coresight_cti_reg(chinstatus, CTICHINSTATUS), coresight_cti_reg(choutstatus, CTICHOUTSTATUS), #ifdef CONFIG_CORESIGHT_CTI_INTEGRATION_REGS coresight_cti_reg_rw(itctrl, CORESIGHT_ITCTRL), coresight_cti_reg(ittrigin, ITTRIGIN), + coresight_cti_reg(ittrigin1, CTI_REG_SET_NR_CONST(ITTRIGIN, 1)), + coresight_cti_reg(ittrigin2, CTI_REG_SET_NR_CONST(ITTRIGIN, 2)), + coresight_cti_reg(ittrigin3, CTI_REG_SET_NR_CONST(ITTRIGIN, 3)), coresight_cti_reg(itchin, ITCHIN), coresight_cti_reg_rw(ittrigout, ITTRIGOUT), + coresight_cti_reg_rw(ittrigout1, CTI_REG_SET_NR_CONST(ITTRIGOUT, 1)), + coresight_cti_reg_rw(ittrigout2, CTI_REG_SET_NR_CONST(ITTRIGOUT, 2)), + coresight_cti_reg_rw(ittrigout3, CTI_REG_SET_NR_CONST(ITTRIGOUT, 3)), coresight_cti_reg_rw(itchout, ITCHOUT), coresight_cti_reg(itchoutack, ITCHOUTACK), coresight_cti_reg(ittrigoutack, ITTRIGOUTACK), + coresight_cti_reg(ittrigoutack1, CTI_REG_SET_NR_CONST(ITTRIGOUTACK, 1)), + coresight_cti_reg(ittrigoutack2, CTI_REG_SET_NR_CONST(ITTRIGOUTACK, 2)), + coresight_cti_reg(ittrigoutack3, CTI_REG_SET_NR_CONST(ITTRIGOUTACK, 3)), coresight_cti_reg_wo(ittriginack, ITTRIGINACK), + coresight_cti_reg_wo(ittriginack1, CTI_REG_SET_NR_CONST(ITTRIGINACK, 1)), + coresight_cti_reg_wo(ittriginack2, CTI_REG_SET_NR_CONST(ITTRIGINACK, 2)), + coresight_cti_reg_wo(ittriginack3, CTI_REG_SET_NR_CONST(ITTRIGINACK, 3)), coresight_cti_reg_wo(itchinack, ITCHINACK), #endif NULL, @@ -534,10 +552,50 @@ static umode_t coresight_cti_regs_is_visible(struct kobject *kobj, { struct device *dev = kobj_to_dev(kobj); struct cti_drvdata *drvdata = dev_get_drvdata(dev->parent); + static const char * const qcom_suffix_registers[] = { + "triginstatus", + "trigoutstatus", +#ifdef CONFIG_CORESIGHT_CTI_INTEGRATION_REGS + "ittrigin", + "ittrigout", + "ittriginack", + "ittrigoutack", +#endif + }; + int i, nr, max_bank; + size_t len; if (attr == &dev_attr_asicctl.attr && !drvdata->config.asicctl_impl) return 0; + /* + * Banked regs are exposed as (nr = 1..3). + * - Hide them on standard CTIs. + * - On QCOM CTIs, hide suffixes beyond the number of banks implied + * by nr_trig_max (32 triggers per bank). + */ + for (i = 0; i < ARRAY_SIZE(qcom_suffix_registers); i++) { + len = strlen(qcom_suffix_registers[i]); + + if (strncmp(attr->name, qcom_suffix_registers[i], len)) + continue; + + if (kstrtoint(attr->name + len, 10, &nr)) + continue; + + if (!drvdata->is_qcom_cti) + return 0; + + if (nr < 1 || nr > 3) + return 0; + + max_bank = DIV_ROUND_UP(drvdata->config.nr_trig_max, 32) - 1; + if (nr > max_bank) + return 0; + + break; + } + return attr->mode; } -- 2.43.0