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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-82f8ec24850sm33004008b3a.60.2026.04.27.03.05.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 27 Apr 2026 03:05:40 -0700 (PDT) From: Anvesh Jain P Date: Mon, 27 Apr 2026 15:34:54 +0530 Subject: [PATCH v8 3/6] arm64: dts: qcom: glymur-crd: Add Embedded controller node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260427-add-driver-for-ec-v8-3-702f74e495f7@oss.qualcomm.com> References: <20260427-add-driver-for-ec-v8-0-702f74e495f7@oss.qualcomm.com> In-Reply-To: <20260427-add-driver-for-ec-v8-0-702f74e495f7@oss.qualcomm.com> To: Sibi Sankar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Bryan O'Donoghue , Bjorn Andersson , Konrad Dybcio , Randy Dunlap Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org, Anvesh Jain P , Dmitry Baryshkov , Konrad Dybcio , Abel Vesa X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1777284317; l=1650; i=anvesh.p@oss.qualcomm.com; s=20260313; h=from:subject:message-id; bh=3BLnT5OTOT0qEyowVKSfm/R3DNxg4MouTyG+K4wg5xE=; b=Hlbo3xq6s5a6jr3USS+Pcqn+F0iHwlc9CIYWbC2511TyN1Y1eaq6TwYcu+raC6WosoM7rMxuU zYss128YWnKAfipuhrCrQmJjeOKmKfnQOH+rmrv9oeWf3jsSnIJATaN X-Developer-Key: i=anvesh.p@oss.qualcomm.com; a=ed25519; pk=8o9EG7gkPe2Er9y9UVCx8MTdcFCwU8Pa54hBZPuduXE= X-Proofpoint-GUID: uMlJBCNJThwylIPaiIU5si38gtkrJQCM X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI3MDEwNSBTYWx0ZWRfX06pfZkeH9Dvg FkHNNc5/6v6MzoTQj8jRLnGnKfh3lCdGiI2fdIQ/eevgwkrtpWIuX80uZBqrvOVNRfIXw+aUjkS AmrfMv8xGj2W0RGkU7/lIPKvXTGDMmCn+QgPfmKQyxz+t3GK7emWKPmndWPXQojRVX6veNWArOU 5XY1OFplS/KGfuNiYTdyZ+WicV2ChTnLtB02Rh/xcSavAFm+++A5ZUqScGh6wiC2ri5x1jwsM70 QBcVHJL4ZC565xM6cebfMK7fEExVQ+IWWsRJsuPHNN2QCpG2TTSdPiPw97EZKrtq5QrRpW/CgYn MQPFqyUWydpv4A2nciZWXDLCZwuPnc+zUlLoaEfi08mzvLJ9r13xSL+rmtsXkynv6A4XysbhGW0 bu+B3R6f18BxtdLxEeAaFitlmMBvTE4BGzhi6ClgiKFXvZS+vTVgsSGqVSp2RQc+SQw4V7uThqn ybZQK0JH/DZkE5TJq3Q== X-Proofpoint-ORIG-GUID: uMlJBCNJThwylIPaiIU5si38gtkrJQCM X-Authority-Analysis: v=2.4 cv=J/GaKgnS c=1 sm=1 tr=0 ts=69ef34f6 cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=h-fhkJo0eXD2C244oGgA:9 a=QEXdDO2ut3YA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-27_03,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 impostorscore=0 priorityscore=1501 adultscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604270105 From: Sibi Sankar Add embedded controller node for Glymur CRDs which adds fan control, temperature sensors, access to EC state changes through SCI events and suspend entry/exit notifications to the EC. Signed-off-by: Sibi Sankar Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Co-developed-by: Anvesh Jain P Signed-off-by: Anvesh Jain P --- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi index 2852d257ac8c..8f684f3402ba 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dtsi @@ -433,6 +433,22 @@ vreg_l4h_e0_1p2: ldo4 { }; }; +&i2c9 { + clock-frequency = <400000>; + + status = "okay"; + + embedded-controller@76 { + compatible = "qcom,glymur-crd-ec", "qcom,hamoa-crd-ec"; + reg = <0x76>; + + interrupts-extended = <&tlmm 66 IRQ_TYPE_EDGE_FALLING>; + + pinctrl-0 = <&ec_int_n_default>; + pinctrl-names = "default"; + }; +}; + &pcie3b { vddpe-3v3-supply = <&vreg_nvmesec>; @@ -565,6 +581,12 @@ &tlmm { <10 2>, /* OOB UART */ <44 4>; /* Security SPI (TPM) */ + ec_int_n_default: ec-int-n-state { + pins = "gpio66"; + function = "gpio"; + bias-disable; + }; + pcie4_default: pcie4-default-state { clkreq-n-pins { pins = "gpio147"; -- 2.34.1