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Sun, 26 Apr 2026 23:39:48 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-361410a7ab7sm38628234a91.10.2026.04.26.23.39.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 26 Apr 2026 23:39:47 -0700 (PDT) From: Taniya Das Date: Mon, 27 Apr 2026 12:09:00 +0530 Subject: [PATCH v2 6/6] drm/msm/a6xx: Limit GXPD votes to recovery in A8x Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260427-gfx-clk-fixes-v2-6-797e54b3d464@oss.qualcomm.com> References: <20260427-gfx-clk-fixes-v2-0-797e54b3d464@oss.qualcomm.com> In-Reply-To: <20260427-gfx-clk-fixes-v2-0-797e54b3d464@oss.qualcomm.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Konrad Dybcio , Abel Vesa , Rob Clark , Sean Paul , Konrad Dybcio , Akhil P Oommen , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Authority-Analysis: v=2.4 cv=aqCCzyZV c=1 sm=1 tr=0 ts=69ef04b5 cx=c_pps a=0uOsjrqzRL749jD1oC5vDA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=wUjT8lVc3dO_4AMqBZcA:9 a=QEXdDO2ut3YA:10 a=mQ_c8vxmzFEMiUWkPHU9:22 X-Proofpoint-GUID: R8a7rhOzH4IwAtM6QjxbvE7NhGi8mmcm X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI3MDA2OCBTYWx0ZWRfX2YaRWnaeunrR KrTHjfhezRDikZVInaHsEgb+PV7BXP9Z+WKwfJsr6kk3aW2pDI13ubPrBu6eRted809/MMt1bFz bMtssd0mwAaG+9csDRIQ/eEzMWTBuzSrVpy8jMyX3woYrIwiljLXtr+t8iWOtGP07V5It9tXI+3 3TGNQSdm3ClG6PTsIzjK4xcZs1rMOnwqfa4Bp5dvQbA3YRyzu7kv57fVS1Eku5N4Ej2K6I9QMBq 6tAZFvoAM9zfgr5R01nXOJYrxt0rJ0X/FVHbCwoEfAPfGTIUMdpn2h1W+ERVkCiWtGOzGPsy7MX P75IC8tF5HkhJ1Z6bFFepM+3oVAUOAqqpjoByWkSbkxbKvzMP/k7ePj0dAI0dyEpwMV76jZ05bm ikHJszlSC3ynNhy6GUhEKasHL3DIaXfHgruDh52Cd8UE4MXMwRTfjLWeNfORgKtw8MH3npEmS4p 0RA8VhLIva+Y2ZEBIqw== X-Proofpoint-ORIG-GUID: R8a7rhOzH4IwAtM6QjxbvE7NhGi8mmcm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-27_01,2026-04-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 phishscore=0 spamscore=0 adultscore=0 suspectscore=0 malwarescore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604270068 From: Akhil P Oommen In A8x GPUs, the GX GDSC is moved to a separate block called GXCLKCTL which is under the GX power domain. Due to the way the support for this block is implemented in its driver, pm_runtime votes result in a vote on GX/GMxC/MxC rails from the APPS RSC. This is against the Adreno architecture which require GMU to be the sole voter of these collapsible rails on behalf of GPU, except during the GPU/GMU recovery. To align with this architectural requirement and to realize the power benefits of the IFPC feature, remove the GXPD votes during gmu resume and suspend. And during the recovery sequence, enable/disable the GXPD along with the 'synced_poweroff' genpd hint to force collapse this GDSC. Signed-off-by: Akhil P Oommen Signed-off-by: Taniya Das --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 64 +++++++++++++++++++++++++++++------ 1 file changed, 54 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 1b44b9e21ad868e6454b9140284cc7ebedc4f59a..b7166a883b018f459caae742e9a589f32167f8d2 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -1250,6 +1250,56 @@ static int a6xx_gmu_secure_init(struct a6xx_gpu *a6xx_gpu) return 0; } +static int a6xx_gmu_gxpd_get(struct a6xx_gmu *gmu) +{ + struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; + + if (IS_ERR_OR_NULL(gmu->gxpd)) + return 0; + + /* + * On A8xx HW, GX GDSC is moved to a new clk controller block under GX + * power domain. The clock driver for this new block keeps the GX rail + * voted when gxpd is voted. So, use the gxpd only during gpu recovery. + */ + if (adreno_gpu->info->family >= ADRENO_8XX_GEN1) + return 0; + + /* + * On A6x/A7x, "enable" the GX power domain which won't actually do + * anything but it will make sure that the refcounting is correct in + * case we need to bring down the GX after a GMU failure + */ + return pm_runtime_get_sync(gmu->gxpd); +} + +static int a6xx_gmu_gxpd_put(struct a6xx_gmu *gmu) +{ + struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); + struct adreno_gpu *adreno_gpu = &a6xx_gpu->base; + + if (IS_ERR_OR_NULL(gmu->gxpd)) + return 0; + + if (adreno_gpu->info->family < ADRENO_8XX_GEN1) + return pm_runtime_put_sync(gmu->gxpd); + + /* + * On A8x, GX GDSC collapse should be triggered only when it is stuck ON + */ + if (adreno_gpu->funcs->gx_is_on(adreno_gpu)) { + pm_runtime_get_sync(gmu->gxpd); + /* + * Hint to gfxclkctl driver to do a hw collapse during the next + * RPM PUT. This is a special behavior in the gfxclkctl driver + */ + dev_pm_genpd_synced_poweroff(gmu->gxpd); + pm_runtime_put_sync(gmu->gxpd); + } + + return 0; +} int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) { @@ -1266,13 +1316,7 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) /* Turn on the resources */ pm_runtime_get_sync(gmu->dev); - /* - * "enable" the GX power domain which won't actually do anything but it - * will make sure that the refcounting is correct in case we need to - * bring down the GX after a GMU failure - */ - if (!IS_ERR_OR_NULL(gmu->gxpd)) - pm_runtime_get_sync(gmu->gxpd); + a6xx_gmu_gxpd_get(gmu); /* Use a known rate to bring up the GMU */ clk_set_rate(gmu->core_clk, 200000000); @@ -1339,7 +1383,8 @@ int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu) disable_clk: clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); rpm_put: - pm_runtime_put(gmu->gxpd); + a6xx_gmu_gxpd_put(gmu); + pm_runtime_put(gmu->dev); return ret; @@ -1455,8 +1500,7 @@ int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu) * domain. Usually the GMU does this but only if the shutdown sequence * was successful */ - if (!IS_ERR_OR_NULL(gmu->gxpd)) - pm_runtime_put_sync(gmu->gxpd); + a6xx_gmu_gxpd_put(gmu); clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks); -- 2.34.1