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charset="utf-8" Content-Transfer-Encoding: 8bit Message-Id: <20260427-visionox-rm69299-enable-v1-1-fa7d62d26d87@sigxcpu.org> References: <20260427-visionox-rm69299-enable-v1-0-fa7d62d26d87@sigxcpu.org> In-Reply-To: <20260427-visionox-rm69299-enable-v1-0-fa7d62d26d87@sigxcpu.org> To: Neil Armstrong , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter Cc: dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org, David Heidelberg , =?utf-8?q?Guido_G=C3=BCnther?= X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=4304; i=agx@sigxcpu.org; h=from:subject:message-id; bh=18NYeaQ+mVybiXnZoHTdPXC31Y87nOeJpcTxWS0RO8A=; b=LS0tLS1CRUdJTiBQR1AgTUVTU0FHRS0tLS0tCgpvd0VCYlFLUy9aQU5Bd0FJQVNXL2hsSksvT UhqQWNzbVlnQnA3MnNROVZ6Si9vTWRzczVVdVFpV3dpWG5POEI3CmVWWHNFSzdEdmp3WjRqc1Bo YmVKQWpNRUFBRUlBQjBXSVFSajlzemZsaUtkQ1NocktzTWx2NFpTU3Z6QjR3VUMKYWU5ckVBQUt DUkFsdjRaU1N2ekI0NFJLRUFDTk56Y0VsOEVaRkxkYjZQeEhmTHNCSHIrK0JibWdBM1NoZnBIbQ pub2R3VmxxUVFMTlhBeUZVQ0NyQWpHMHlobWM0VzdvRTlUbU9pN3lMS0xLT3hjYkpXSjJFTFRUS itkcWRnUVl5Ckw2SmhTV0dyeVZCYzJWOTFkbDZuOSs1M25ETWdXWmJYK1BZWGlBeDI2c25BVWJ0 N0JOcDhJeGxNNHprY2phSWUKSXk5dmtLL0VCcmlxVTJVeHpjWVdDTGY4cGNwcnF6T0c2SUJITGF MVHU2dWV5RUZhUFJucTNSRkVyYzFwaEJTSQpmUjgvQzlEcDJwMFdxTzZSZ2ZmRzVSeTJPYlN1Mz d3VHFpWDMvRFFiemg0N2JFdlFZL1NWTFhQbHFwdmp4S2t2CnVLeHpkSTdYVVBsSlFpaC9hemFMT kFiRmo3b0hmS3ZSQVMxVktjeFZJUnZhVFU1eHRERmlZaEhpbmYxZkJOS3kKQ0lOUHZoZE16SVg3 eFBVZnV0bHlQNHA1eCttRThPUWpja1JsbG8xNVAxd3VuaDZXQTZHY2pGODNFa2RaSVdUTQp1eHk 5c2FORDBlS0djWkQ0Unc3Q0o0VEl1VjZKdWUwRWU4dzRCaGM2UitISzhKK0l1VlRsS0h0anBWSF Z4MVUxCkU1Z3R5d2FVbXpoN2JLRVFQNWtYaWRscWQvSVBKOWVwVlhFdFRnOHcrZWZ6aGVQaE55U XVYR09aWGpkWGVlV3IKZXQ0RXFseGlMQndRUjhkYzdzODBuT2Y2cDVGN1g2dXdUd0s1SW5taEtj V25tcjRZMmtVVkYzbnRMY04rSmlxegppQ2toRmZlT0lRTEI1VUNZR3o2eFB2OW5uUUVzb3JQd2R zQW02TGh1Ly9KdDVtN3VxQXVUT3AwYkpxU2N4NXhhCjNFMTNtUT09Cj02bFZMCi0tLS0tRU5EIF BHUCBNRVNTQUdFLS0tLS0K X-Developer-Key: i=agx@sigxcpu.org; a=openpgp; fpr=0DB3932762F78E592F6522AFBB5A2C77584122D3 It's when DSI commands should be sent and it also fixes these DSI errors on every screen blank/unblank on the SHIFT6mq: dmesg: msm_dsi ae94000.dsi: [drm:dsi_cmds2buf_tx] *ERROR* wait for video done timed out dsi_cmds2buf_tx: cmd dma tx failed, type=0x5, data0=0x28, len=4, ret=-110 panel-visionox-rm69299 ae94000.dsi.0: sending DCS SET_DISPLAY_OFF failed: -110 Signed-off-by: Guido Günther --- drivers/gpu/drm/panel/panel-visionox-rm69299.c | 77 +++++++++++++++----------- 1 file changed, 44 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/panel/panel-visionox-rm69299.c b/drivers/gpu/drm/panel/panel-visionox-rm69299.c index f1430370ff94..3c92a6ceb8df 100644 --- a/drivers/gpu/drm/panel/panel-visionox-rm69299.c +++ b/drivers/gpu/drm/panel/panel-visionox-rm69299.c @@ -158,6 +158,46 @@ static inline struct visionox_rm69299 *panel_to_ctx(struct drm_panel *panel) return container_of(panel, struct visionox_rm69299, panel); } +static int visionox_rm69299_enable(struct drm_panel *panel) +{ + struct visionox_rm69299 *ctx = panel_to_ctx(panel); + struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; + + ctx->dsi->mode_flags |= MIPI_DSI_MODE_LPM; + + for (int i = 0; i < ctx->desc->init_seq_len; i++) + mipi_dsi_dcs_write_buffer_multi(&dsi_ctx, &ctx->desc->init_seq[i * 2], 2); + + mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); + + /* Per DSI spec wait 120ms after sending exit sleep DCS command */ + mipi_dsi_msleep(&dsi_ctx, 120); + + mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); + + /* Per DSI spec wait 120ms after sending set_display_on DCS command */ + mipi_dsi_msleep(&dsi_ctx, 120); + + return dsi_ctx.accum_err; +} + +static int visionox_rm69299_disable(struct drm_panel *panel) +{ + struct visionox_rm69299 *ctx = panel_to_ctx(panel); + struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; + + ctx->dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; + + mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); + + /* 120ms delay required here as per DCS spec */ + mipi_dsi_msleep(&dsi_ctx, 120); + + mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); + + return dsi_ctx.accum_err; +} + static int visionox_rm69299_power_on(struct visionox_rm69299 *ctx) { int ret; @@ -193,16 +233,6 @@ static int visionox_rm69299_power_off(struct visionox_rm69299 *ctx) static int visionox_rm69299_unprepare(struct drm_panel *panel) { struct visionox_rm69299 *ctx = panel_to_ctx(panel); - struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; - - ctx->dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; - - mipi_dsi_dcs_set_display_off_multi(&dsi_ctx); - - /* 120ms delay required here as per DCS spec */ - mipi_dsi_msleep(&dsi_ctx, 120); - - mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx); return visionox_rm69299_power_off(ctx); } @@ -210,29 +240,8 @@ static int visionox_rm69299_unprepare(struct drm_panel *panel) static int visionox_rm69299_prepare(struct drm_panel *panel) { struct visionox_rm69299 *ctx = panel_to_ctx(panel); - struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; - int ret, i; - ret = visionox_rm69299_power_on(ctx); - if (ret < 0) - return ret; - - ctx->dsi->mode_flags |= MIPI_DSI_MODE_LPM; - - for (i = 0; i < ctx->desc->init_seq_len; i++) - mipi_dsi_dcs_write_buffer_multi(&dsi_ctx, &ctx->desc->init_seq[i * 2], 2); - - mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx); - - /* Per DSI spec wait 120ms after sending exit sleep DCS command */ - mipi_dsi_msleep(&dsi_ctx, 120); - - mipi_dsi_dcs_set_display_on_multi(&dsi_ctx); - - /* Per DSI spec wait 120ms after sending set_display_on DCS command */ - mipi_dsi_msleep(&dsi_ctx, 120); - - return dsi_ctx.accum_err; + return visionox_rm69299_power_on(ctx); } static const struct drm_display_mode visionox_rm69299_1080x2248_60hz = { @@ -284,7 +293,9 @@ static int visionox_rm69299_get_modes(struct drm_panel *panel, static const struct drm_panel_funcs visionox_rm69299_drm_funcs = { .unprepare = visionox_rm69299_unprepare, - .prepare = visionox_rm69299_prepare, + .disable = visionox_rm69299_disable, + .prepare = visionox_rm69299_prepare, + .enable = visionox_rm69299_enable, .get_modes = visionox_rm69299_get_modes, }; -- 2.53.0