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Fix this by adding 48MHz clock support for pll_p_out1 along with 48MHz support for pll_a, main pll_p_out1 descendant. --- Changes in v2: - aligned with downstream 3.4 kernel for tegra114 logic --- Dmitry Osipenko (1): clk: tegra: support 48MHz clock for pll_p_out1 drivers/clk/tegra/clk-pll.c | 1 + 1 file changed, 1 insertion(+) -- 2.51.0