From: Qiang Ma <maqianga@uniontech.com>
To: chenhuacai@kernel.org, kernel@xen0n.name
Cc: loongarch@lists.linux.dev, linux-kernel@vger.kernel.org,
Qiang Ma <maqianga@uniontech.com>
Subject: [PATCH] LoongArch: Correct the definitions related to CSR_CPUID_COREID{_WIDTH}
Date: Tue, 28 Apr 2026 20:35:10 +0800 [thread overview]
Message-ID: <20260428123510.314073-1-maqianga@uniontech.com> (raw)
The valid bits of CPU Identity (CPUID) are 0 to 8
according to LoongArch Reference Manual, so change
11 to 9 for the related code.
Link: https://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#cpu-identity
Signed-off-by: Qiang Ma <maqianga@uniontech.com>
---
arch/loongarch/include/asm/loongarch.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
index 2a6bc99177d8..bc47df90fee6 100644
--- a/arch/loongarch/include/asm/loongarch.h
+++ b/arch/loongarch/include/asm/loongarch.h
@@ -429,8 +429,8 @@
/* Config CSR registers */
#define LOONGARCH_CSR_CPUID 0x20 /* CPU core id */
-#define CSR_CPUID_COREID_WIDTH 11
-#define CSR_CPUID_COREID _ULCAST_(0x7ff)
+#define CSR_CPUID_COREID_WIDTH 9
+#define CSR_CPUID_COREID _ULCAST_(0x1ff)
#define LOONGARCH_CSR_PRCFG1 0x21 /* Config1 */
#define CSR_CONF1_VSMAX_SHIFT 12
--
2.20.1
next reply other threads:[~2026-04-28 12:36 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-28 12:35 Qiang Ma [this message]
2026-04-28 12:47 ` Huacai Chen
2026-04-28 13:16 ` Qiang Ma
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