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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-364bd588ad5sm66732a91.3.2026.04.29.08.24.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Apr 2026 08:24:33 -0700 (PDT) From: Kathiravan Thirumoorthy Subject: [PATCH v2 0/4] Add minimal boot support for Qualcomm IPQ9650 SoC Date: Wed, 29 Apr 2026 20:54:21 +0530 Message-Id: <20260429-ipq9650_boot_to_shell-v2-0-9b0dc3d1f3a8@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAKUi8mkC/3WPzW6DMBCEXwX5XEf+wSZw6ntUEVqbpbiCONgGJ Yp49xpStadeVjvS7HyzTxIxOIykKZ4k4Oqi89csxFtB7ADXT6Suy5oIJjSTklF3m2utWGu8T23 ybRxwHClXNRNVp8qztSTf3gL27n7kflxeOi7mC23aw34cAeclA9PL9sfL+IMm9C8tjdNEBXCLU Ore1rxZ+Z5iICK1fppcagrU2IOxDHoLTORdaAkGlJS9VF3NOK/AiLMke6PBxeTD43g8Z+0FDmr J1T8/rpwyamSFprQSeMfffYyneYFxL3DKg1y2bfsGxPiNiFMBAAA= X-Change-ID: 20260330-ipq9650_boot_to_shell-159027d548cc To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Kathiravan Thirumoorthy , Krzysztof Kozlowski X-Mailer: b4 0.15.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1777476269; l=2587; i=kathiravan.thirumoorthy@oss.qualcomm.com; s=20230906; h=from:subject:message-id; bh=h51VaY30oVcgyb7vKdtI6o+pR2fhhkIjNYTH8SmpLGE=; b=2hG2KNlQlYc43LOvAu+LsUXlN8aSGKMmZnVCRA86UUf/9x6yN0vWxB55QvPmHtVml2Ke8H10G +gVBIbNdvudCoqFgEp4/VSUvZNRqq8u9U3iGlM7Oqi8HPy+iSM3p/1O X-Developer-Key: i=kathiravan.thirumoorthy@oss.qualcomm.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Proofpoint-GUID: 49XMFkGycG7JrTLfxUU6gaCY5zrAN8dD X-Proofpoint-ORIG-GUID: 49XMFkGycG7JrTLfxUU6gaCY5zrAN8dD X-Authority-Analysis: v=2.4 cv=Wak8rUhX c=1 sm=1 tr=0 ts=69f222b4 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=bC-a23v3AAAA:8 a=YURS4O9UCPS1-Wi1IM0A:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 a=FO4_E8m0qiDe52t0p3_H:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI5MDE1NSBTYWx0ZWRfX+u+PAQc9C85l YDUdrp3FSrYiNXQoyveNC2f4Il/Xw8egpp8wZcuyOpMZ2dxredkPinyfw08G7M3vpyhOLbPMfsO DoA42rkzGWMtOhPWay83FHN+Ve7Du45G7oCr1augTkaQxFNtRj0dj0ammx0fP22fxZZMlS+IYZZ fT4CPNJNFfgM/A8FSfwhrPxj9mUvrZnlCcSsRtyNefmCuTMdgeFvpnctbmt+aJeSOQZ/eyqTgmZ M7N+PQzcm4ia2PVzq4eeSm2yfcxTQ6fPC1mbidsgOSinGxwiITEcmcLn6zYIBz+1Wd7NeGZgCfD s2OyCpiHfGYQB1TAxoucjEQ3OuVzDM7wQ4a0XjklrTe0gHokslXV+9Y1ejkfieDUeRKkNu8CjT0 34vE4+sxexAo4NI4i3S1LlCvDgntfRCzYgDCt7ifW7vweRqcBiBGlknqlaxuwnvT0HyVrBkkN3j UzyRbLUg+zI+sRhwrRQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-29_01,2026-04-28_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 spamscore=0 clxscore=1015 bulkscore=0 impostorscore=0 adultscore=0 phishscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604290155 Qualcomm IPQ9650 is a networking SoC targeted at routers, gateways, and access points. This change adds minimal support required to boot the IPQ9650 RDP488 board. Compared to earlier IPQ SoCs, IPQ9650 features a heterogeneous CPU configuration with four Cortex-A55 cores and one Cortex-A78 core, a 2 MB shared L3 cache, SMMU support, IPCC, five PCIe Gen3 controllers, an integrated CDSP for task offloading, enhanced PPE capabilities, and DDR5 memory support. More information can be found at the product page: https://docs.qualcomm.com/doc/87-96766-1/87-96766-1_REV_AA_Qualcomm_Dragonwing_NPro_A8_Elite_Platform_Product_Brief.pdf Signed-off-by: Kathiravan Thirumoorthy --- Changes in v2: - Collected the R-b tags - Add the ARM64 dependency to the GCC driver and enable it by default to align with Krzysztof's effort to cleanup the defconfig - Updated the GICv3 interrupt-cells to 4 and added the ppi-partitions and hooked up with the PMU instances. - Made the labels to lower case and kept the \n before status property - Dropped the defconfig patch - Link to v1: https://patch.msgid.link/20260415-ipq9650_boot_to_shell-v1-0-b37eb4c3a1d1@oss.qualcomm.com --- Kathiravan Thirumoorthy (4): dt-bindings: clock: add Qualcomm IPQ9650 GCC clk: qcom: add Global Clock controller (GCC) driver for IPQ9650 SoC dt-bindings: qcom: add IPQ9650 boards arm64: dts: qcom: add IPQ9650 SoC and rdp488 board support Documentation/devicetree/bindings/arm/qcom.yaml | 5 + .../bindings/clock/qcom,ipq9650-gcc.yaml | 68 + arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/ipq9650-rdp488.dts | 79 + arch/arm64/boot/dts/qcom/ipq9650.dtsi | 376 ++ drivers/clk/qcom/Kconfig | 10 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-ipq9650.c | 3795 ++++++++++++++++++++ include/dt-bindings/clock/qcom,ipq9650-gcc.h | 190 + include/dt-bindings/reset/qcom,ipq9650-gcc.h | 228 ++ 10 files changed, 4753 insertions(+) --- base-commit: e6efabc0afca02efa263aba533f35d90117ab283 change-id: 20260330-ipq9650_boot_to_shell-159027d548cc prerequisite-change-id: 20260326-ipq9650_tlmm-2a1cea46fc91:v1 prerequisite-patch-id: 13d4c96c03378602b50fa7a976e57f97f960b018 prerequisite-patch-id: fcc2de8f1b615b06fe2e509bdcb1ffd719274dc6 Best regards, -- Kathiravan Thirumoorthy