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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-12de321df36sm7572644c88.7.2026.04.29.20.21.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Apr 2026 20:21:43 -0700 (PDT) From: Linlin Zhang To: linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, ebiggers@google.com Cc: neeraj.soni@oss.qualcomm.com, gaurav.kashyap@oss.qualcomm.com, deepti.jaggi@oss.qualcomm.com, bjorn.andersson@oss.qualcomm.com, quic_shazhuss@quicinc.com, trilok.soni@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com, Deepti Jaggi Subject: [PATCH v6 3/3] soc: qcom: ice: Add SCMI support for sa8255p based targets Date: Wed, 29 Apr 2026 20:21:35 -0700 Message-Id: <20260430032136.3058773-4-linlin.zhang@oss.qualcomm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260430032136.3058773-1-linlin.zhang@oss.qualcomm.com> References: <20260430032136.3058773-1-linlin.zhang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: iti8wJe8WUrjqtwTJfzJZxpBQ7OkwRfa X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDMwMDAzMCBTYWx0ZWRfX5cIZxDIP+u4A e+fZ3Q2UxnYAg52ljM4W/chMR1kBW+8xkJMRB1WnXjKO9S2ywxlUmnk+OGbKoI0Ht9Xm0luanP8 eDMIxi9b4QxVzztak04Hirf5tLdjSmY7p5uyWK65aNsj5iLHQxLzrCDq5K1o5+6Q39KrdHIh8Mb eCRZp48vHTpoYVGAJPU/N26L2Asj01yXkM9lfG/MXaINe+RX6fU+3JrcIcdhIlnhWCYwoazqAk+ c2IR/wkePhw9NUQJEaYcKjqQaOP4n6AgihbFsZZzRsRQ4xurP9CWUGl8S+ntVkvV3lYQLZ4lUlG cRL8jjk6RISas6G5ObEjIPmdjXYmf19WtN3Tdu1jmejfLhiZgeQK3G00/3a2dj82Ep5rQvyyGLy i4V3Czf0+cDTCPoRwfWeDF/u9KZaU78sfIhYrEkuQ52lG54M62hr0M1aDRfBQHVz4vpKAPzbWQC UNrk8fEPSqvvQ0NoMGQ== X-Proofpoint-ORIG-GUID: iti8wJe8WUrjqtwTJfzJZxpBQ7OkwRfa X-Authority-Analysis: v=2.4 cv=PvmjqQM3 c=1 sm=1 tr=0 ts=69f2cac9 cx=c_pps a=bS7HVuBVfinNPG3f6cIo3Q==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=SaV-z_UyVCyeOftNReQA:9 a=vBUdepa8ALXHeOFLBtFW:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-30_01,2026-04-28_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 spamscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604300030 The Qualcomm automotive SA8255p SoC relies on firmware to configure platform resources, including clocks, interconnects and TLMM. The driver requests resources operations over SCMI using power and performance protocols. The SCMI power protocol enables or disables resources like clocks, interconnect paths, and TLMM (GPIOs) using runtime PM framework APIs, such as resume/suspend, to control power states(on/off). The SCMI performance protocol manages ICE clock, with a power domain set for ICE clock. The driver uses runtime PM framework APIs to request power on/off status of the clock. Reviewed-by: Neeraj Soni Reviewed-by: Deepti Jaggi Signed-off-by: Linlin Zhang --- drivers/soc/qcom/ice.c | 64 ++++++++++++++++++++++++++++-------------- 1 file changed, 43 insertions(+), 21 deletions(-) diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c index 6f9d679b530c..cf185a6e1973 100644 --- a/drivers/soc/qcom/ice.c +++ b/drivers/soc/qcom/ice.c @@ -68,6 +68,10 @@ union crypto_cfg { }; }; +struct engine_desc { + bool fw_managed; +}; + /* QCOM ICE HWKM (Hardware Key Manager) registers */ #define HWKM_OFFSET 0x8000 @@ -554,6 +558,7 @@ static struct qcom_ice *qcom_ice_create(struct device *dev, void __iomem *base) { struct qcom_ice *engine; + const struct engine_desc *engine_cfg = NULL; if (!qcom_scm_is_available()) return ERR_PTR(-EPROBE_DEFER); @@ -570,20 +575,23 @@ static struct qcom_ice *qcom_ice_create(struct device *dev, engine->dev = dev; engine->base = base; - /* - * Legacy DT binding uses different clk names for each consumer, - * so lets try those first. If none of those are a match, it means - * the we only have one clock and it is part of the dedicated DT node. - * Also, enable the clock before we check what HW version the driver - * supports. - */ - engine->core_clk = devm_clk_get_optional_enabled(dev, "ice_core_clk"); - if (!engine->core_clk) - engine->core_clk = devm_clk_get_optional_enabled(dev, "ice"); - if (!engine->core_clk) - engine->core_clk = devm_clk_get_enabled(dev, NULL); - if (IS_ERR(engine->core_clk)) - return ERR_CAST(engine->core_clk); + engine_cfg = device_get_match_data(dev); + if (!engine_cfg || !engine_cfg->fw_managed) { + /* + * Legacy DT binding uses different clk names for each consumer, + * so lets try those first. If none of those are a match, it means + * the we only have one clock and it is part of the dedicated DT node. + * Also, enable the clock before we check what HW version the driver + * supports. + */ + engine->core_clk = devm_clk_get_optional_enabled(dev, "ice_core_clk"); + if (!engine->core_clk) + engine->core_clk = devm_clk_get_optional_enabled(dev, "ice"); + if (!engine->core_clk) + engine->core_clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(engine->core_clk)) + return ERR_CAST(engine->core_clk); + } if (!qcom_ice_check_supported(engine)) return ERR_PTR(-EOPNOTSUPP); @@ -756,13 +764,17 @@ static void qcom_ice_remove(struct platform_device *pdev) static int ice_runtime_resume(struct device *dev) { - struct qcom_ice *ice = dev_get_drvdata(dev); + struct engine_desc *engine_cfg = device_get_match_data(dev); int err = 0; - err = clk_prepare_enable(ice->core_clk); - if (err) { - dev_err(dev, "failed to enable core clock (%d)\n", - err); + if (!engine_cfg || !engine_cfg->fw_managed) { + struct qcom_ice *ice = dev_get_drvdata(dev); + + err = clk_prepare_enable(ice->core_clk); + if (err) { + dev_err(dev, "failed to enable core clock (%d)\n", + err); + } } return err; @@ -770,9 +782,14 @@ static int ice_runtime_resume(struct device *dev) static int ice_runtime_suspend(struct device *dev) { - struct qcom_ice *ice = dev_get_drvdata(dev); + const struct engine_desc *engine_cfg = device_get_match_data(dev); + + if (!engine_cfg || !engine_cfg->fw_managed) { + struct qcom_ice *ice = dev_get_drvdata(dev); + + clk_disable_unprepare(ice->core_clk); + } - clk_disable_unprepare(ice->core_clk); return 0; } @@ -780,8 +797,13 @@ static const struct dev_pm_ops ice_pm_ops = { SET_RUNTIME_PM_OPS(ice_runtime_suspend, ice_runtime_resume, NULL) }; +static const struct engine_desc cfg_fw_managed = { + .fw_managed = true, +}; + static const struct of_device_id qcom_ice_of_match_table[] = { { .compatible = "qcom,inline-crypto-engine" }, + { .compatible = "qcom,sa8255p-inline-crypto-engine", .data = &cfg_fw_managed }, { }, }; MODULE_DEVICE_TABLE(of, qcom_ice_of_match_table); -- 2.34.1