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[60.242.93.14]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-834ed80df96sm3595073b3a.54.2026.04.29.21.59.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Apr 2026 21:59:06 -0700 (PDT) From: Lachlan Hodges To: johannes@sipsolutions.net, Lachlan Hodges , Dan Callaghan , Arien Judge Cc: ayman.grais@morsemicro.com, linux-wireless@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH wireless-next v2 29/31] wifi: mm81x: add yaps_hw.h Date: Thu, 30 Apr 2026 14:55:55 +1000 Message-ID: <20260430045615.334669-30-lachlan.hodges@morsemicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260430045615.334669-1-lachlan.hodges@morsemicro.com> References: <20260430045615.334669-1-lachlan.hodges@morsemicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit (Patches split per file for review, will be a single commit alongside SDIO ids once review is complete. See cover letter for more information) Signed-off-by: Lachlan Hodges --- .../net/wireless/morsemicro/mm81x/yaps_hw.h | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 drivers/net/wireless/morsemicro/mm81x/yaps_hw.h diff --git a/drivers/net/wireless/morsemicro/mm81x/yaps_hw.h b/drivers/net/wireless/morsemicro/mm81x/yaps_hw.h new file mode 100644 index 000000000000..89e15375aabc --- /dev/null +++ b/drivers/net/wireless/morsemicro/mm81x/yaps_hw.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2026 Morse Micro + */ + +#ifndef _MM81X_YAPS_HW_H_ +#define _MM81X_YAPS_HW_H_ + +#include +#include + +#define MM81X_INT_YAPS_FC_PKT_WAITING_IRQN 0 +#define MM81X_INT_YAPS_FC_PACKET_FREED_UP_IRQN 1 + +struct mm81x_yaps_hw_table { + /* NOTE: We need these padding bytes for yaps to work */ + u8 padding[4]; + __le32 ysl_addr; + __le32 yds_addr; + __le32 status_regs_addr; + + /* Alloc pool sizes */ + __le16 tc_tx_pool_size; + __le16 fc_rx_pool_size; + u8 tc_cmd_pool_size; + u8 tc_beacon_pool_size; + u8 tc_mgmt_pool_size; + u8 fc_resp_pool_size; + u8 fc_tx_sts_pool_size; + u8 fc_aux_pool_size; + + /* To chip/from chip queue sizes */ + u8 tc_tx_q_size; + u8 tc_cmd_q_size; + u8 tc_beacon_q_size; + u8 tc_mgmt_q_size; + u8 fc_q_size; + u8 fc_done_q_size; + + __le16 yaps_reserved_page_size; + __le16 reserved_unused; +} __packed; + +struct mm81x; + +void mm81x_yaps_hw_enable_irqs(struct mm81x *mors, bool enable); +int mm81x_yaps_hw_init(struct mm81x *mors); +void mm81x_yaps_hw_finish(struct mm81x *mors); +void mm81x_yaps_hw_read_table(struct mm81x *mors, + struct mm81x_yaps_hw_table *tbl_ptr); + +#endif /* !_MM81X_YAPS_HW_H_ */ -- 2.43.0