From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pf1-f176.google.com (mail-pf1-f176.google.com [209.85.210.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 10C3B36681F for ; Thu, 30 Apr 2026 04:57:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.176 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777525024; cv=none; b=LeCK6Aw/KIDNIge+dMBBGv+QC1UxW+KCKj1w5rjGDfaUvYwq0qsGX32vDmxdUPGJmWwAL1x7YtMTVdfEON3Z3nYWDUoVhejI3c6iPat0Ouu75GXWQEdVvJ495QKLuVo4faOGf+XPvGB5C7Zbuo8wdWmFXYffyqgpuM2aet0Xo1c= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777525024; c=relaxed/simple; bh=9TyB8vv5bdZStr/Q1niVBjRaeWUcL3/nyNMQiiUXakk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=U/8/nPrbCHrS+MkCmratDJo5j8uHs2E1maHbWnFs3gAyTiqqyOvKjlGtaOrRlXpcDGKR4hX+AZK61rVxhEJtkmeTypGj3U0lhtM1RhcScC58S58YWo/Dc4/V+xgy4BUxYD9l+ow9CDSB5kHryeX6qx0LR5qYAHt4yHn/QB9kR3E= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=morsemicro.com; spf=pass smtp.mailfrom=morsemicro.com; dkim=pass (2048-bit key) header.d=morsemicro-com.20251104.gappssmtp.com header.i=@morsemicro-com.20251104.gappssmtp.com header.b=jjOrYJ8/; arc=none smtp.client-ip=209.85.210.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=morsemicro.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=morsemicro.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=morsemicro-com.20251104.gappssmtp.com header.i=@morsemicro-com.20251104.gappssmtp.com header.b="jjOrYJ8/" Received: by mail-pf1-f176.google.com with SMTP id d2e1a72fcca58-82d0b68837aso271124b3a.2 for ; Wed, 29 Apr 2026 21:57:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=morsemicro-com.20251104.gappssmtp.com; s=20251104; t=1777525022; x=1778129822; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nVCjz/fVhCFpjcMt+RPvID80Nomp20lkcFEvzXdhCJA=; b=jjOrYJ8/+jMN13F12diwGLblWvZyKJgCyWmLYhamQSBOI2UJ4mDNOj0OOSW1UTBs5n +tgwBHXhDSjgXG8Yc6Nb9m6o0zuhrCaGMI49Oa2cWPk+5/2sx5saASuH+QmM/+Sq9Qnb mnz7pd0Dpc4Jwz1USR5QDkfgLcZPrjtqzyR/Pkukf3yF/NhpDIZubJ2huwrQsDpRRYC7 znzVzX71A7385b4M0eEZnCObjRdHU4fdHPd6givyE5csuV+l1Zs+WJiBgZpnqkhv6fw/ k//qRBZB0jj8KQOCSHQqJEQfjM67kScdZiPWCOvh/t6rFzvZnjLtWu4cIswRRnXo+D6K BhEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777525022; x=1778129822; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=nVCjz/fVhCFpjcMt+RPvID80Nomp20lkcFEvzXdhCJA=; b=hrxode4YWH/E3X8WiT2ngzTKQCd/elJePvZXuHK5G0S36WTqcNFg0Q3xbmhiTZCnV5 WI07HSB3uaa2A6khBLrgPEC4QQ6tJ9KZITGdcTezMRxZCP//+c7RR+XIkJF0T0Fmn//N rCBwS/0KMqVdSzO8z9l9JyFHDW3qEEVZP4+1oAxiFjnTk+jWFwzX2n+pOz1CxOkSnpdm dk4AklMgWT0Yf9ob4JJBMKdHZVagzUOzn619SGu/yyrOatSC9J+sVAzBU3qgNTXlhg1t xyDvzJx72Qxc/IDfEGcZMMTXSTv0LW2VlC5bULUWR7uA8GvW+WMRWzcNE1KulQalbbPZ GSiQ== X-Forwarded-Encrypted: i=1; AFNElJ/HNYLfcwJ66h7RWX+HTlJ/u/xNm9Cal1LhxvK7w5+d//u2m1oj/4L6Fw3zk+I7xG8AWnWx2EQ0DGbwdlw=@vger.kernel.org X-Gm-Message-State: AOJu0YxsHAvkKrA5o6fp6stiSEOAKOtOXLNSpJ0kDKE0L6keC57kpZgE 9zTCzFJr2/mrS4d4r477ll92ad3VNNqotbCP4WXtG+NNBv9k3UY1hyoiqGPGxW/O4d0= X-Gm-Gg: AeBDietkhPxSOtFH/xEhmv3tDmim0ri2GC/Z8j9SoqDU69dlGMUy8Zq5pQYzDi4fFCS Jjxd3Z2J/9dNSu6FNHNCtpyinY9C8B17Nrsfk51sy/Q0v/S3tfedQVAiETNkLL4ljui+PsgnBVP 8jUTQHF6mFEyDMigjfrdGq3BHPyvn+Nb2soOSMiE0S/LlCFmWheQ+dM8pTE6I/afz9X1jBxnjOo 1mI0IvmICWLT8Eyr1Kn8vLyOzffzY4WaotI6wWK87Gdx3F/328blvcDlGS2sDzOxZbQTvZcfaG5 94xTE4N6z0IPmiWI/nX1aeEVeufKsFZZeNqHGW6R92n02qIpHU04fX+EQe+lIrmfwy2lnIIueKK aeZqnXFQ7FH/rjlcgNG/qWpDBUQH3YybfY3oAgh1PyrBP23NVBdAMRNyUnet8acFcVM7/5FFQ9E v56jJjGgAFRP9JZNEIJWlOwMiIlMdRKp8eOQM7o4BtdzwI7+RygeLX2QbsADS1zqrzTMj+k4Syn LBvFtSNJ04VTdoXwkJccS8IOo0ddxUxXXUzerc0Vw== X-Received: by 2002:a05:6a00:2441:b0:82f:6be8:6c0e with SMTP id d2e1a72fcca58-834fdc8d5d6mr1686595b3a.45.1777525021994; Wed, 29 Apr 2026 21:57:01 -0700 (PDT) Received: from mma-H9MHD44.lan (60-242-93-14.static.tpgi.com.au. [60.242.93.14]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-834ed80df96sm3595073b3a.54.2026.04.29.21.56.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Apr 2026 21:57:01 -0700 (PDT) From: Lachlan Hodges To: johannes@sipsolutions.net, Lachlan Hodges , Dan Callaghan , Arien Judge Cc: ayman.grais@morsemicro.com, linux-wireless@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH wireless-next v2 05/31] wifi: mm81x: add core.c Date: Thu, 30 Apr 2026 14:55:31 +1000 Message-ID: <20260430045615.334669-6-lachlan.hodges@morsemicro.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260430045615.334669-1-lachlan.hodges@morsemicro.com> References: <20260430045615.334669-1-lachlan.hodges@morsemicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit (Patches split per file for review, will be a single commit alongside SDIO ids once review is complete. See cover letter for more information) Signed-off-by: Lachlan Hodges --- drivers/net/wireless/morsemicro/mm81x/core.c | 146 +++++++++++++++++++ 1 file changed, 146 insertions(+) create mode 100644 drivers/net/wireless/morsemicro/mm81x/core.c diff --git a/drivers/net/wireless/morsemicro/mm81x/core.c b/drivers/net/wireless/morsemicro/mm81x/core.c new file mode 100644 index 000000000000..b08f52921525 --- /dev/null +++ b/drivers/net/wireless/morsemicro/mm81x/core.c @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2017-2026 Morse Micro + */ +#include +#include "core.h" +#include "bus.h" +#include "hif.h" +#include "mac.h" + +char board_config_file[BCF_SIZE_MAX] = ""; +module_param_string(bcf, board_config_file, BCF_SIZE_MAX, 0644); +MODULE_PARM_DESC(bcf, "BCF filename to load"); + +static int mm81x_core_attach_regs(struct mm81x *mors) +{ + int ret = 0; + + mm81x_claim_bus(mors); + ret = mm81x_reg32_read(mors, MM8108_REG_CHIP_ID, &mors->chip_id); + mm81x_release_bus(mors); + + if (ret < 0) { + dev_err(mors->dev, "failed to read chip id %d", ret); + return ret; + } + + switch (mors->chip_id) { + case (MM8108B2_ID): + mors->regs = &mm8108_regs; + mors->hif.ops = &mm81x_yaps_ops; + break; + default: + return -ENODEV; + } + + return ret; +} + +static char *mm81x_core_get_revision_string(u32 chip_id) +{ + u8 chip_rev = MM81X_DEVICE_GET_CHIP_REV(chip_id); + + switch (chip_rev) { + case MM8108B2_REV: + return MM8108B2_REV_STRING; + default: + return "??"; + } +} + +static void mm81x_core_init_mac_addr(struct mm81x *mors) +{ + int ret = mm81x_hw_otp_get_mac_addr(mors); + + if (ret || !is_valid_ether_addr(mors->macaddr)) + eth_random_addr(mors->macaddr); +} + +char *mm81x_core_get_fw_path(u32 chip_id) +{ + return kasprintf(GFP_KERNEL, + MM81X_FW_DIR "/" MM8108_FW_BASE + "%s" FW_ROM_LINKED_STRING MM81X_FW_EXT, + mm81x_core_get_revision_string(chip_id)); +} +EXPORT_SYMBOL_GPL(mm81x_core_get_fw_path); + +struct mm81x *mm81x_core_alloc(size_t priv_size, struct device *dev) +{ + return mm81x_mac_alloc(priv_size, dev); +} +EXPORT_SYMBOL_GPL(mm81x_core_alloc); + +int mm81x_core_init(struct mm81x *mors) +{ + int ret; + + set_bit(MM81X_STATE_CHIP_UNRESPONSIVE, &mors->state_flags); + set_bit(MM81X_STATE_RELOAD_FW_AFTER_START, &mors->state_flags); + + mm81x_core_init_mac_addr(mors); + + ret = mm81x_core_attach_regs(mors); + if (ret) + return ret; + + mors->chip_wq = create_singlethread_workqueue("chip_wq"); + if (!mors->chip_wq) + return -ENOMEM; + + mors->net_wq = create_singlethread_workqueue("net_wq"); + if (!mors->net_wq) { + ret = -ENOMEM; + goto err_chip_wq; + } + + ret = mm81x_hif_init(mors); + if (ret) + goto err_wqs; + + return 0; + +err_wqs: + flush_workqueue(mors->net_wq); + destroy_workqueue(mors->net_wq); + +err_chip_wq: + flush_workqueue(mors->chip_wq); + destroy_workqueue(mors->chip_wq); + + return ret; +} +EXPORT_SYMBOL_GPL(mm81x_core_init); + +int mm81x_core_register(struct mm81x *mors) +{ + return mm81x_mac_register(mors); +} +EXPORT_SYMBOL_GPL(mm81x_core_register); + +void mm81x_core_unregister(struct mm81x *mors) +{ + mm81x_mac_unregister(mors); +} +EXPORT_SYMBOL_GPL(mm81x_core_unregister); + +void mm81x_core_deinit(struct mm81x *mors) +{ + mm81x_hif_finish(mors); + flush_workqueue(mors->net_wq); + destroy_workqueue(mors->net_wq); + flush_workqueue(mors->chip_wq); + destroy_workqueue(mors->chip_wq); +} +EXPORT_SYMBOL_GPL(mm81x_core_deinit); + +void mm81x_core_free(struct mm81x *mors) +{ + mm81x_mac_free(mors); +} +EXPORT_SYMBOL_GPL(mm81x_core_free); + +MODULE_AUTHOR("Morse Micro"); +MODULE_DESCRIPTION("Driver support for Morse Micro MM81X core"); +MODULE_LICENSE("Dual BSD/GPL"); -- 2.43.0