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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Bxj9zFLZiiUm+Ba8yuIjCM5LBo4IKg/Yto6NWApQWcS+X3MX2xT1Jj41zwazY0IcDsaeLqzn8VHXroaXnXWef8RHKUMN430RbHlgHpWDlNtDoxNJCQhLsD5zGqpIM0wJkpXpQ+9RQBnRRb3Wc3BVcgUHfDzBWxt5XSo56s3s+zL+ProZTQelHaljLew7dFrlV+rG8v70PNPgLiZdo4oNiEBvFA6DJh6yy8eIJsF/tI0nHr0VxqKPdQstjldd2q8ab15g43790xEG5n3xMJpXMsGpRsWV+uSxH2q7ELHsFir8XmXYr8dfzhZ09pkdQyecW4WbOX4k0WY+6kJHbLmYGowoWHr9QRX2mAVrqAzqbK2wLbWpl2ZvyW8cugRCqNVXcMip16rPYN/qRj4I8GiSJOc+kgBLHMfAb3RazlbWrhoUGcZkC8FNCvmAUQYDD7NY X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2026 15:35:01.1919 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4124ffc2-eb8d-4143-b0e6-08dea6ce0b19 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00027A65.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AMDPR08MB11553 LPIs are owned by the LPI domain, so allocating and freeing them from the ITS MSI and IPI domains was always a bit backwards. Those domains should only ask their parent for interrupts, and never need to know how the parent picks or releases the underlying LPIs (or do it on behalf of said parent, as was the case). This series moves LPI allocation into the LPI domain itself and removes the exported wrappers that allowed LPI allocation from elsewhere. With that done, the LPI domain can also be slightly reworked to support allocating and freeing more than one LPI at a time. This rework is extended to the IPI allocation, too. The last patch makes the ITS MSI domain request its parent interrupts as a single range, matching the IPI cleanup from the previous patch. As a side effect of these changes, the IPI path now unwinds earlier parent allocations correctly if a later allocation fails. Thanks, Sascha Sascha Bischoff (3): irqchip/gic-v5: Move LPI alloc/free into LPI domain irqchip/gic-v5: Allow for nr_irqs > 1 for LPI alloc and teardown irqchip/gic-v5: Allocate ITS parent LPIs as a range drivers/irqchip/irq-gic-v5-its.c | 34 +++-------- drivers/irqchip/irq-gic-v5.c | 90 ++++++++++++++++-------------- include/linux/irqchip/arm-gic-v5.h | 3 - 3 files changed, 56 insertions(+), 71 deletions(-) --=20 2.34.1=