From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D11093A7835 for ; Tue, 5 May 2026 17:12:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.11.138.130 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778001148; cv=none; b=cf8irdpgOMkpXZWiCTikqZoqimLS3VyYzvKEEfDcUONQKLFoHG/zy9DW32NthM1lqb6elSjmKCELht3fGRJWbHPeVAv3hRUSUBNLdWudDFPmxhpryaB/J2ScZJsyS5XF0COiBlBKFQu+Io5NL650uN5DXmZ2cI+zTk/v51iRmNQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778001148; c=relaxed/simple; bh=ojh9eB98gYSMnvTUgSXMn2Zw0/ZSIkKVn/YDNliV2iM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GiOExhamrC14KQ7OqlD+ZJHo7OCZRnkYtBtKhMQ6BY2XddvZVxkWJcgA0MPkZLkt/bTsEjJCCzdyNPrDWnxY+FtIut5oz97OPdPGpcegUb6cHmI3K0KblX14O7ZpCrzN3ot3PUwilWOzRdK02woPVq1Y8up7q5+H2w9bJV+PJTY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=sntech.de; spf=pass smtp.mailfrom=sntech.de; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b=ztqPZS1Q; arc=none smtp.client-ip=185.11.138.130 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=sntech.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sntech.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=sntech.de header.i=@sntech.de header.b="ztqPZS1Q" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sntech.de; s=gloria202408; h=Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Reply-To:Content-Type; bh=P0+N+OKN/kTVkUzotmztG3kumJS+495ukG6sbMOmjcY=; b=ztqPZS1QYDXHebO2xYBa4ILcpc VDzgwBuYXww8q80OfL9ezXMzItO2DNkbHnlB7kuTRK9elBGuSJMdTVnhzCCOA9fWyfvUjIl4N4oMG fJO7nZmhm7vjW6m8+xQXVXK+rk1fJO/YsmPMIiyNtKOr4EWlETUunO926LB8bVxDLxD3csQTbkbjO GhA52z+xeRuSDr2EtRxInMvHEp3Qe97s6SCws4RaRTr3CmMW399tSGfbPZ9aeVfNNpGybDdlm+Elg p5c7dRAJGcF4lLmy6iMnGxU8X3BvY1fSOyLt4aMANsOKYfZ/LRMAiyAe7N9j0q5bX7dHSLdhNSp+k /rcplN5A==; From: Heiko Stuebner To: heiko@sntech.de Cc: jonas@kwiboo.se, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/5] arm64: dts: rockchip: Add USB nodes for RK3528 Date: Tue, 5 May 2026 19:12:04 +0200 Message-ID: <20260505171208.3267387-2-heiko@sntech.de> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260505171208.3267387-1-heiko@sntech.de> References: <20260505171208.3267387-1-heiko@sntech.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Jonas Karlman Rockchip RK3528 has one USB 3.0 DWC3 controller and oneUSB 2.0 EHCI/OHCI controller and uses an Innosilicon-USB2PHY for USB 2.0. The DWC3 controller additionally uses the Naneng Combo PHY for USB3. Add device tree nodes to describe these USB controllers along with the USB 2.0 PHYs. Signed-off-by: Jonas Karlman Signed-off-by: Heiko Stuebner --- arch/arm64/boot/dts/rockchip/rk3528.dtsi | 77 ++++++++++++++++++++++++ 1 file changed, 77 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3528.dtsi b/arch/arm64/boot/dts/rockchip/rk3528.dtsi index 806b8109f67d..8823df18f66e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3528.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3528.dtsi @@ -336,6 +336,30 @@ pcie_intc: legacy-interrupt-controller { }; }; + usb_host0_xhci: usb@fe500000 { + compatible = "rockchip,rk3528-dwc3", "snps,dwc3"; + reg = <0x0 0xfe500000 0x0 0x400000>; + clocks = <&cru CLK_REF_USB3OTG>, + <&cru CLK_SUSPEND_USB3OTG>, + <&cru ACLK_USB3OTG>; + clock-names = "ref_clk", "suspend_clk", "bus_clk"; + interrupts = ; + power-domains = <&power RK3528_PD_VPU>; + resets = <&cru SRST_A_USB3OTG>; + dr_mode = "otg"; + phy_type = "utmi_wide"; + snps,dis_enblslpm_quirk; + snps,dis_rxdet_inp3_quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,parkmode-disable-hs-quirk; + snps,parkmode-disable-ss-quirk; + status = "disabled"; + }; + gic: interrupt-controller@fed01000 { compatible = "arm,gic-400"; reg = <0x0 0xfed01000 0 0x1000>, @@ -349,6 +373,30 @@ gic: interrupt-controller@fed01000 { #interrupt-cells = <3>; }; + usb_host0_ehci: usb@ff100000 { + compatible = "generic-ehci"; + reg = <0x0 0xff100000 0x0 0x40000>; + clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>, + <&usb2phy>; + interrupts = ; + phys = <&usb2phy_host>; + phy-names = "usb"; + power-domains = <&power RK3528_PD_VO>; + status = "disabled"; + }; + + usb_host0_ohci: usb@ff140000 { + compatible = "generic-ohci"; + reg = <0x0 0xff140000 0x0 0x40000>; + clocks = <&cru HCLK_USBHOST>, <&cru HCLK_USBHOST_ARB>, + <&usb2phy>; + interrupts = ; + phys = <&usb2phy_host>; + phy-names = "usb"; + power-domains = <&power RK3528_PD_VO>; + status = "disabled"; + }; + qos_crypto_a: qos@ff200000 { compatible = "rockchip,rk3528-qos", "syscon"; reg = <0x0 0xff200000 0x0 0x20>; @@ -1273,6 +1321,35 @@ combphy: phy@ffdc0000 { rockchip,pipe-phy-grf = <&pipe_phy_grf>; status = "disabled"; }; + + usb2phy: usb2phy@ffdf0000 { + compatible = "rockchip,rk3528-usb2phy"; + reg = <0x0 0xffdf0000 0x0 0x10000>; + clocks = <&cru CLK_REF_USBPHY>, <&cru PCLK_USBPHY>; + clock-names = "phyclk", "pclk"; + #clock-cells = <0>; + clock-output-names = "clk_usbphy_480m"; + power-domains = <&power RK3528_PD_VO>; + rockchip,usbgrf = <&vo_grf>; + status = "disabled"; + + usb2phy_otg: otg-port { + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + + usb2phy_host: host-port { + interrupts = ; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + }; }; }; -- 2.47.3