From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-qk1-f170.google.com (mail-qk1-f170.google.com [209.85.222.170]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F067F30EF6C for ; Wed, 6 May 2026 19:09:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.222.170 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778094551; cv=none; b=d26bhqkAAAwQKNejQAwVPOxidVwPCMbwLLEuMYQ/EmKXZEbHAvVf2uPkgVzR2DwloEurzPguOOc8pLM5VX5UmK4+occBsFI7MPQbYwKAQmn17YXV0er4xm7BZTo5M6ewkaYBQ4+tYlQ5jsf8N4A9sssK8UJGIOV7RXRqtWMRMy0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778094551; c=relaxed/simple; bh=Wqj6Yz67iE9Ok+wJC8tz2MHMdpWmQX+GsmU1u2KkQkk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KgmBffelOba66NYO78DzXrgE4W7CycMdf1SCyik9SDT4iQNbxYI+1JFjdijAovvZcLXUK6kW3VcjdgM055LAbe/UcGsYGJZkfKBydPQ+J4rX6Vjyk+Bw6QGDI9YZhS/PqpME0JFbfKLSAcH6hRGyFwBv+ZDM6okT77im81jhnEE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=gZOg9p9O; arc=none smtp.client-ip=209.85.222.170 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="gZOg9p9O" Received: by mail-qk1-f170.google.com with SMTP id af79cd13be357-8ef2118b478so5846585a.0 for ; Wed, 06 May 2026 12:09:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1778094549; x=1778699349; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=miWAgzkhPxRPUhdzmqfb98aKwIPZoZcraPxTFPB+VJc=; b=gZOg9p9O4ej6QQp2Ovb0xWMo9VxanAR5lMOkURGSCb4ehVvK0Dq0TJQ4kebY3e9CW1 epBBGd9v6XR0Gjmq8b2mTi5six+jbYOKYEbsdVg0gmvY7IPC6UsqzBCZy3eI3plinTfm UflgChPYMJ4iaJ/0yfVEHSx915yNuKagqbD2n96Au+0eVc/qmzfn2Y8FI4jHV+OYMZJG g7qs3BRaw7M3NCM/ALiaDYe+/5kf2KdCQVd8rc3Wi+XCjIN2uzQopju3t6bTx2xZOE4k CcrUZNeVWaYrSn2+WtFmfHIzMN6z3kq8o1F988e/Lhji6kZqSRHG6GdPz+/bgnWFtRtM yGGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778094549; x=1778699349; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=miWAgzkhPxRPUhdzmqfb98aKwIPZoZcraPxTFPB+VJc=; b=EeRsf8eeJmb11FcEe5zPdwXXEWKkftuJBKRC3aWqu1XQeAcslr31iJtFQvUEz/YDOz jqxJ9XvdhuT8Yvy3gRtcminVzbfNXT0/Pn5bO8bu/QnQBP3ZL3Z9hzA/s4DG9/3eulZR k8GlMPCq1KDETSEaWfRWOvDRdugf0+z66e5zN/ozC6FtYXQApkWOJArQAEl8oyqHK978 /0mP3q6tcdRWv5rCl8tEcsG7Frahd14qMHd0t3B2p8Oz8UjaTeLT1gAQnGZSpXJVUNho Dr8MgTS67nlyChxSbAcqRz7m4OU5G6oDYYcPumNBxlOGl+oHLxGZVrIyVxqAXsSpKpU2 bpHA== X-Forwarded-Encrypted: i=1; AFNElJ8/oGdfgO/U29eXvEu6AZdsyv9lLp1dU/irYksuuEDiePNDazpaqueDlbeH8GyuVuxv8H4arbk54mHndiM=@vger.kernel.org X-Gm-Message-State: AOJu0YzoAPrvxjiw4I8ouWE0vO1P/NqX16fa9dc2462pfoGfdfVHkqOe kyu2y86vC+FnBs+ItpZlLm5L6cbOq6Iz0pDu+3ij/qZhw4u0oNwAqg76 X-Gm-Gg: AeBDiet/SY/u5r5Qse9+iRxd5zrBtQMF7gExjKaDuae95MYfqCP2L3P+f+T0fU/Sm4/ bKga1T+UEecZiwV2Bc++GbTgWytfMhRkWO8awtGa2d9VS7PwTK2Aduc2T01La0nGE37vhxLpDCd U+2d+ytYCqIJAkmdmjMuZXR8BGvh86SprA80STykBznJp6Ge+MIhfUUqETBUWdRKib3c4LDmBmU QSvpumXwOG31wNRnCbkUSVQTEz2LiLYvTejMfHTGRzxVz8obSxVO4cOw2hVLRyBX0YKdGGsyBNO WHnKbTZh391NhtxMsX7yYucaszgLEXcWE1IrFpFtOi3cDaLD53+qVFtgbVU5lVF0YMEAL/IH0Vu EweNAtUn9DH03TA36vA7VFebXGXacWxrUBOp6HHrzb9Hgk9QFNOtrroQdqjpLsFFvjyjuz1/cbw ll5fjWoJPBme8sJ1MyXCZz9TOqTsrCHwIu+Z2YEgrEf8sWvS0/jcVi74uWvMCtOub8ihQ= X-Received: by 2002:a05:622a:4ac7:b0:50b:4e4e:1a20 with SMTP id d75a77b69052e-514621c747cmr69868341cf.59.1778094548753; Wed, 06 May 2026 12:09:08 -0700 (PDT) Received: from PF5YBGDS.localdomain ([163.114.130.1]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-5104090bb03sm157489421cf.10.2026.05.06.12.09.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 06 May 2026 12:09:08 -0700 (PDT) From: mike.marciniszyn@gmail.com To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Alexander Duyck , Kees Cook Cc: mike.marciniszyn@gmail.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 2/2] net: pcs: xpcs: Add handling for 4 channel rsfec device Date: Wed, 6 May 2026 15:09:04 -0400 Message-ID: <20260506190904.4029-3-mike.marciniszyn@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260506190904.4029-1-mike.marciniszyn@gmail.com> References: <20260506190904.4029-1-mike.marciniszyn@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: "Mike Marciniszyn (Meta)" This patch introduces the configuration of vendor specific registers for alignment encoding, PCS Mode, and VL_INTVL over the one or two instances as required. The DW_PCS IP specification calls out the need to configure both lanes identically when using 2 lane modes such as 50-R2 and 100-R2, so the programming is repeated for each lane. The encoding tables are derived from the IEEE 8023-2022 spec sections 82.2.7 and tables 82-2 and 82-3 for the alignment markers and their insertion. Note that there is a conflict between VRs DW_VR_XS_PCS_DIG_STS and and the DW_PCS_IP DW_VR_MII_PCS_PCS_MODE. The bit mask for DW_VR_XS_PCS_DIG_STS/RX_FIFO_ERR fits within the reserved bits for the DW_PCS IP the DW_VR_MII_PCS_PCS_MODE register so there is no issue. There is also a confict between DW_VR_MII_PCS_VL_INTVL and DW_VR_MII_AN_INTR_STS but an_mode differs, so again there is no issue. Reviewed-by: Alexander Duyck Signed-off-by: Mike Marciniszyn (Meta) --- drivers/net/pcs/pcs-xpcs.c | 90 +++++++++++++++++++++++++++++++++++++- drivers/net/pcs/pcs-xpcs.h | 25 +++++++++++ 2 files changed, 114 insertions(+), 1 deletion(-) diff --git a/drivers/net/pcs/pcs-xpcs.c b/drivers/net/pcs/pcs-xpcs.c index 0987621632a7..c42eacafad91 100644 --- a/drivers/net/pcs/pcs-xpcs.c +++ b/drivers/net/pcs/pcs-xpcs.c @@ -1429,21 +1429,94 @@ static int xpcs_get_pma_mmd(struct dw_xpcs *xpcs) return -ENODEV; } +/* m0 - m2 from Table 82-2/82-3 + * m4 - m6 are skipped since they are inversions of m0 - m2. + * Inverted parity fields (IEEE 82.2.8) bip3 and bip7 are omitted. + */ +struct lane_markers { + u8 m0, m1, m2; +}; + +/* Alignment marker encodings, see table 82-2 in IEEE 802.3-2022 */ +static const struct lane_markers xpcs_100gbaser_markers[] = { + {0xc1, 0x68, 0x21}, + {0x9d, 0x71, 0x8e}, + {0x59, 0x4b, 0xe8}, + {0x4d, 0x95, 0x7b}, +}; + +/* Alignment marker encodings, see table 82-3 in IEEE 802.3-2022 + * The content of the 50G markers is identical to 40G values (IEEE 133.2.2). + */ +static const struct lane_markers xpcs_50gbaser_markers[] = { + {0x90, 0x76, 0x47}, + {0xf0, 0xc4, 0xe6}, + {0xc5, 0x65, 0x9b}, + {0xa2, 0x79, 0x3d}, +}; + struct pma_pcs_values { + const struct lane_markers *vl0_markers; + const struct lane_markers *vl123_markers; int lanes; u16 rsfec_ctrl; + u16 pcs_mode; + u16 vl_intvl; }; +#define XPCS_VL_TO_REG(vl, lh) \ + (((vl) * 2) + DW_VR_MII_PCS_VL0_##lh) + +static int xpcs_write_pcs_prtad(struct dw_xpcs *xpcs, int prtad, int reg, + u16 val) +{ + return xpcs_bus_write(xpcs, prtad, MDIO_MMD_PCS, reg, val); +} + +static int xpcs_config_vl_markers(struct dw_xpcs *xpcs, int vl, int addr, + const struct lane_markers *m) +{ + int ret; + + /* m0, m1, m2 written to _L and _H registers + * + * _L = (m1 << 8) | m0 + * _H = m2 + */ + ret = xpcs_write_pcs_prtad(xpcs, addr, XPCS_VL_TO_REG(vl, L), + ((u16)m->m1 << 8) | m->m0); + if (ret < 0) + return ret; + return xpcs_write_pcs_prtad(xpcs, addr, XPCS_VL_TO_REG(vl, H), m->m2); +} + static int xpcs_config_rsfec_pma(struct dw_xpcs *xpcs, const struct pma_pcs_values *v) { - int ret = 0, i, pma_mmd; + int ret = 0, i, vl, pma_mmd; pma_mmd = xpcs_get_pma_mmd(xpcs); if (pma_mmd < 1) return pma_mmd; for (i = 0; ret >= 0 && i < v->lanes; i++) { + /* code word markings */ + for (vl = 0; ret >= 0 && vl < 4; vl++) + ret = xpcs_config_vl_markers(xpcs, vl, i, + !vl ? &v->vl0_markers[0] : + &v->vl123_markers[vl - 1]); + if (ret < 0) + break; + /* vendor registers */ + ret = xpcs_write_pcs_prtad(xpcs, i, DW_VR_MII_PCS_VL_INTVL, + v->vl_intvl); + if (ret < 0) + break; + ret = xpcs_write_pcs_prtad(xpcs, i, DW_VR_MII_PCS_PCS_MODE, + v->pcs_mode); + if (ret < 0) + break; + /* rsfec register */ ret = xpcs_bus_write(xpcs, i, pma_mmd, MDIO_PMA_RSFEC_CTRL, v->rsfec_ctrl); } @@ -1455,6 +1528,13 @@ static int xpcs_25gbaser_pma_config(struct dw_xpcs *xpcs) const struct pma_pcs_values v = { .rsfec_ctrl = 0, .lanes = 1, + /* 25g markers from 100g and 50g tables per 802.3-2022 + * 108.5.2.4 + */ + .vl0_markers = &xpcs_100gbaser_markers[0], + .vl123_markers = &xpcs_50gbaser_markers[1], + .vl_intvl = 20479, + .pcs_mode = DW_VR_MII_PCS_MODE_CLAUSE107, }; return xpcs_config_rsfec_pma(xpcs, &v); @@ -1465,6 +1545,10 @@ static int xpcs_50gbaser_pma_config(struct dw_xpcs *xpcs) const struct pma_pcs_values v = { .rsfec_ctrl = DW_VR_RSFEC_CTRL_TC_PAD_ALTER, .lanes = 2, + .vl0_markers = &xpcs_50gbaser_markers[0], + .vl123_markers = &xpcs_50gbaser_markers[1], + .pcs_mode = 0, + .vl_intvl = 20479, }; return xpcs_config_rsfec_pma(xpcs, &v); @@ -1475,6 +1559,10 @@ static int xpcs_100gbasep_pma_config(struct dw_xpcs *xpcs) const struct pma_pcs_values v = { .rsfec_ctrl = MDIO_PMA_RSFEC_CTRL_4LANE_PMD, .lanes = 2, + .vl0_markers = &xpcs_100gbaser_markers[0], + .vl123_markers = &xpcs_100gbaser_markers[1], + .pcs_mode = DW_VR_MII_PCS_MODE_DISABLE_MLD, + .vl_intvl = 16383, }; return xpcs_config_rsfec_pma(xpcs, &v); diff --git a/drivers/net/pcs/pcs-xpcs.h b/drivers/net/pcs/pcs-xpcs.h index 187cdec30e70..8161d75370e6 100644 --- a/drivers/net/pcs/pcs-xpcs.h +++ b/drivers/net/pcs/pcs-xpcs.h @@ -100,6 +100,31 @@ */ #define DW_VR_RSFEC_CTRL_TC_PAD_ALTER BIT(10) +/* Vendor specific 4 channel PCS registers */ + +/* DW_VR_MII_PCS_VL_INTVL and DW_VR_MII_AN_INTR_STS conflict + * but code paths are different + */ +#define DW_VR_MII_PCS_VL_INTVL 0x8002 +/* 0x8008 - 0x800f */ +#define DW_VR_MII_PCS_VL0_L 0x8008 +#define DW_VR_MII_PCS_VL0_H 0x8009 +#define DW_VR_MII_PCS_PCS_MODE 0x8010 + +/* DW_VR_MII_PCS_PCS_MODE bits */ +#define DW_VR_MII_PCS_MODE_HI_BER25 BIT(2) +#define DW_VR_MII_PCS_MODE_DISABLE_MLD BIT(1) +#define DW_VR_MII_PCS_MODE_CLAUSE49 BIT(0) + +/* 25G requires these two bits are set. + * + * The CLAUSE49 bit changes the interface with the MAC + * to 64 bit and the BER25 bit changes the measurement + * interval to 2ms. + */ +#define DW_VR_MII_PCS_MODE_CLAUSE107 \ + (DW_VR_MII_PCS_MODE_HI_BER25 | DW_VR_MII_PCS_MODE_CLAUSE49) + #define DW_XPCS_INFO_DECLARE(_name, _pcs, _pma) \ static const struct dw_xpcs_info _name = { .pcs = _pcs, .pma = _pma } -- 2.43.0