From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5158C348452 for ; Thu, 7 May 2026 11:26:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778153194; cv=none; b=lQSYHcs6YMHmMgjh4Nzyj8UUZfv1PlqUFVaTBeSGayhk06WHhm/DfAqDO1+wD1CU/BRS1f5QhgxVKXerh3CkBKDn46v9raBfXjiRjq5Ytp2HR969v0rmqiJHBSKirYHYAC4Oi7za0wWM1ug2U7fKXosLxyuvvPPONcpm4BJQP70= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778153194; c=relaxed/simple; bh=NFa6T1OlpES6l8VtfHxFeXgujLOXbuuENS2CTFHA2J0=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Y9d+VL2Vi2SCV4zqWJXv3eQgtGOBDTc6X8D5C9rb9tEYCuBGZdBhtxGy4Ev75XoisNbmDs3/Gl91FNSngPdEOAp/6cwYhY6G7nyOi7IKgEnGpuXd7elzW8tAk5LF3S9mjizOqpf4hMedYusLHTCzBdkHiVTvF3Z5+N/87WPfckA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=BD5ggKdD; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=BERYWr/G; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="BD5ggKdD"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="BERYWr/G" Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 647ANVLF152860 for ; Thu, 7 May 2026 11:26:32 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=UL3C3PYs7qb 8LJc+zdz+SzMOIXkiCyeUwN4vYWoaCaE=; b=BD5ggKdDm9ao69GTgrd2lMeUvrO MrW5qic1WqOQdB5Dg+/b00qmw3gIK4Ntd5wE6umu5Z6d7r402+BG9h0TmI1rU5Xz iN+rm1ZcHeqU4vYdBk+00cw/Z8g6Gukf4MZyTBku/PzqcVsjbst/lYs856+s90gb MRJ9szJqOti7p5hEn0OxFGA4ZCNNo3fF0p9MLY14PkMDblfk0hv7CsdykTufZi5a 0fhg6DKqMOOTCO+AjAEXMxS7wUwsEmv6S22P/erKaI9Q/qKr9ufhyav0v8owvWVC 7V8Uq9ZgWveJB/R9EihOx8qnVNwE9tKbNH/rLzOlwZGPQXjtOmwbxqvuIww== Received: from mail-dy1-f200.google.com (mail-dy1-f200.google.com [74.125.82.200]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4e0kctsk02-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Thu, 07 May 2026 11:26:32 +0000 (GMT) Received: by mail-dy1-f200.google.com with SMTP id 5a478bee46e88-2ba8013a9e3so1083716eec.0 for ; Thu, 07 May 2026 04:26:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1778153191; x=1778757991; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UL3C3PYs7qb8LJc+zdz+SzMOIXkiCyeUwN4vYWoaCaE=; b=BERYWr/GWnLB+SCZnm68htXwkzNePaa+LudLym3Ve2t0jJ1VzBnZS8W1vQnsVpBP5j fgAiHsGUOqsS1nZdabzMPmux6wjVSxXfxATEzH12K0vlDF3Q2SHn6HmcIVHanLCzZGr5 7O8N19+L2JvmXvMlQ4P7Jk8YxUH61wr00R2/rwsylDrPCykgqpJYjqmxUYRVoezEyBWB BNEoIgeS1IdTWrY0uZ46DogOjwJV7AEeSR8ey5PqTCwC9IZ39Ambdk7/9/92x6hT7vve ZrHtRT5wwpDoil1X38Q2UIITN+SMu4LvWiNiabL767ykdw+9eOAlCIF2UDkqpm0aDNmz dKfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778153191; x=1778757991; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=UL3C3PYs7qb8LJc+zdz+SzMOIXkiCyeUwN4vYWoaCaE=; b=Q74XNE7E2nNOW/cJ2CFMvXh4rKqfP/fudP96ruQUB4Fh2xhRB6ODyKmZ1AdD35DO8N Z1bTXZBQLYNiNYNfB4VOOgfSTDyBSWB7kQSe1yYn8WtDkkAGrJBdMMoGTWjNkyP+uA4n mFeiUYBjZ8XwkDzzZeEvxvH8mJirECJl2OcXNyBK+Q5i9OGMTQ4d6iFMnIGIE6Q+EBZq VS9R7yFNuoxwwXxZ7F2TAClvUO2hxEgmi5Kv7mv6TfqjMqJpFGVQoWXkUPjN8WRt3fs0 xn7BzcondRTgasFRUE0mLLnOumpW2Onxq5dX7NAKgoGqYaWa9WKebsP86rj/uBT+oaQc xFYw== X-Forwarded-Encrypted: i=1; AFNElJ/2/XIXPY1D3qZGoT+CBhjiyUgLTDkBDw20ZsZiLl4hPM4gE8XaO3WW6a30qZ9+1Wlgv2G6Rwzyyeb+bjo=@vger.kernel.org X-Gm-Message-State: AOJu0Yw+jqhyHodZAOtskYHCGiFqf1s11ODXqjqclCTaoAsKcTaWnAZG N2dSS611qsCyDpEgb1tHI5ZmjT88Emka8WeB/gdP5XlZ1jI91aAsCQbOr142JSTQSXdeKXXFLMi q6wKTJawulFZQtZAZNALzl9Ssg3ApKr0Lj88UNJgw4JLqnArg5wqEUBCBae8hzlzCTyI= X-Gm-Gg: AeBDievCv9fzNMfgx7tjX6YXqmXnJJ3tWAahi479Oe973w7YHSBUuWBbx9gpf1qDzms KStfDk0Of0qRBg3QJmwPgUjmxGEiZA9JPIYAqBb2WLH10xhEKMhlPh7VXfGl34bPpVoy1sh3jCD TjFljlovHwCY1Vp6CbqDE9udfj4o5WPgV95GQeKoUWk6XD1gxmprVqpc0jgJ7ben3N4IIL/JE6+ PKvlkdHrIPH9/szS0Sbk8OSmWLGtl9Nkltft/+nD8COIXR16lnqHJYpnykbIjQffvOOOVdUfiqz Ulfm6EGoUecZhDI2/cTeXtHFqXoJB+O62IkuFrzFgmZdYmEeyXwKto8Kxw/afCJ9/+ZWMIZt5dn qZh9Dz9Z0FJOefNn7CbK+RkRsR03wfDR/+jVzAuNC9xYqyhECyt5oeipBJYkYd7Q/tf/foCYCoj v+4NMiultSLHDMqMI= X-Received: by 2002:a05:7300:2387:b0:2c1:558c:16e1 with SMTP id 5a478bee46e88-2f54b897efemr3605761eec.4.1778153191364; Thu, 07 May 2026 04:26:31 -0700 (PDT) X-Received: by 2002:a05:7300:2387:b0:2c1:558c:16e1 with SMTP id 5a478bee46e88-2f54b897efemr3605745eec.4.1778153190711; Thu, 07 May 2026 04:26:30 -0700 (PDT) Received: from u20-san1p10573.qualcomm.com (i-global254.qualcomm.com. [199.106.103.254]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2f56fd92780sm8373295eec.23.2026.05.07.04.26.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 May 2026 04:26:30 -0700 (PDT) From: Linlin Zhang To: Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Neeraj Soni , Deepti Jaggi Subject: [PATCH v2 3/3] soc: qcom: ice: Add SCMI support for sa8255p based targets Date: Thu, 7 May 2026 04:26:25 -0700 Message-Id: <20260507112626.2527413-2-linlin.zhang@oss.qualcomm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260507112626.2527413-1-linlin.zhang@oss.qualcomm.com> References: <20260507112626.2527413-1-linlin.zhang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=XsPK/1F9 c=1 sm=1 tr=0 ts=69fc76e8 cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=SaV-z_UyVCyeOftNReQA:9 a=6Ab_bkdmUrQuMsNx7PHu:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: jOBSoYnQ7LjsoUS4_PUxpSU-nxI7NPoR X-Proofpoint-ORIG-GUID: jOBSoYnQ7LjsoUS4_PUxpSU-nxI7NPoR X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA3MDExNCBTYWx0ZWRfX5f+BWCliOy9A 40Ef49xbnGDzcyqn4RGeRYsmO8LPySsLj1GEHJb9qGIgC+GsHcwEcixqf2rhZKk383ZPwpjIiZ7 OavYx5dksPmtYk3vr3+ndT4xuvpNMI480JyTHIW7ReIOdU3cWRRaEJ2fBKp7tav37QGOP3LEvyF 2i9UCNsZOCFnsWlgtDD4M5VOzUB+7vDCloF3svgBvWrmig1lxuujNgMnDI1+g/HhkXPehBdfeMe 8AWXwg7s24+XhVi4dwG+jtXKzyke3kEKFi45IUGVMMXBsiz3XLGy2/0WQzHTg15C2ldlBKV9jqD s7/UyUqhpMRDU1fVQ4OHOP6PZ706Q0WuT6pE+QCymUwxkdj2NdiAZn0sLEvrzK0sKpn8dE0lMml ofRter/eGXKIfV2wzzIEQlCU/8XiYZjIkYWZbTGwCnxOd8TAYp0amvg07/RDYoAHC3XrYT2DiD9 y9Zdpkm78W8YkVPV1cA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-06_02,2026-05-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 adultscore=0 suspectscore=0 phishscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 spamscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605070114 The Qualcomm automotive SA8255p SoC relies on firmware to configure platform resources, including clocks, interconnects and TLMM. The driver requests resources operations over SCMI using power and performance protocols. The SCMI power protocol enables or disables resources like clocks, interconnect paths, and TLMM (GPIOs) using runtime PM framework APIs, such as resume/suspend, to control power states(on/off). The SCMI performance protocol manages ICE clock, with a power domain set for ICE clock. The driver uses runtime PM framework APIs to request power on/off status of the clock. Reviewed-by: Neeraj Soni Reviewed-by: Deepti Jaggi Signed-off-by: Linlin Zhang --- drivers/soc/qcom/ice.c | 64 ++++++++++++++++++++++++++++-------------- 1 file changed, 43 insertions(+), 21 deletions(-) diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c index 6f9d679b530c..cf185a6e1973 100644 --- a/drivers/soc/qcom/ice.c +++ b/drivers/soc/qcom/ice.c @@ -68,6 +68,10 @@ union crypto_cfg { }; }; +struct engine_desc { + bool fw_managed; +}; + /* QCOM ICE HWKM (Hardware Key Manager) registers */ #define HWKM_OFFSET 0x8000 @@ -554,6 +558,7 @@ static struct qcom_ice *qcom_ice_create(struct device *dev, void __iomem *base) { struct qcom_ice *engine; + const struct engine_desc *engine_cfg = NULL; if (!qcom_scm_is_available()) return ERR_PTR(-EPROBE_DEFER); @@ -570,20 +575,23 @@ static struct qcom_ice *qcom_ice_create(struct device *dev, engine->dev = dev; engine->base = base; - /* - * Legacy DT binding uses different clk names for each consumer, - * so lets try those first. If none of those are a match, it means - * the we only have one clock and it is part of the dedicated DT node. - * Also, enable the clock before we check what HW version the driver - * supports. - */ - engine->core_clk = devm_clk_get_optional_enabled(dev, "ice_core_clk"); - if (!engine->core_clk) - engine->core_clk = devm_clk_get_optional_enabled(dev, "ice"); - if (!engine->core_clk) - engine->core_clk = devm_clk_get_enabled(dev, NULL); - if (IS_ERR(engine->core_clk)) - return ERR_CAST(engine->core_clk); + engine_cfg = device_get_match_data(dev); + if (!engine_cfg || !engine_cfg->fw_managed) { + /* + * Legacy DT binding uses different clk names for each consumer, + * so lets try those first. If none of those are a match, it means + * the we only have one clock and it is part of the dedicated DT node. + * Also, enable the clock before we check what HW version the driver + * supports. + */ + engine->core_clk = devm_clk_get_optional_enabled(dev, "ice_core_clk"); + if (!engine->core_clk) + engine->core_clk = devm_clk_get_optional_enabled(dev, "ice"); + if (!engine->core_clk) + engine->core_clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(engine->core_clk)) + return ERR_CAST(engine->core_clk); + } if (!qcom_ice_check_supported(engine)) return ERR_PTR(-EOPNOTSUPP); @@ -756,13 +764,17 @@ static void qcom_ice_remove(struct platform_device *pdev) static int ice_runtime_resume(struct device *dev) { - struct qcom_ice *ice = dev_get_drvdata(dev); + struct engine_desc *engine_cfg = device_get_match_data(dev); int err = 0; - err = clk_prepare_enable(ice->core_clk); - if (err) { - dev_err(dev, "failed to enable core clock (%d)\n", - err); + if (!engine_cfg || !engine_cfg->fw_managed) { + struct qcom_ice *ice = dev_get_drvdata(dev); + + err = clk_prepare_enable(ice->core_clk); + if (err) { + dev_err(dev, "failed to enable core clock (%d)\n", + err); + } } return err; @@ -770,9 +782,14 @@ static int ice_runtime_resume(struct device *dev) static int ice_runtime_suspend(struct device *dev) { - struct qcom_ice *ice = dev_get_drvdata(dev); + const struct engine_desc *engine_cfg = device_get_match_data(dev); + + if (!engine_cfg || !engine_cfg->fw_managed) { + struct qcom_ice *ice = dev_get_drvdata(dev); + + clk_disable_unprepare(ice->core_clk); + } - clk_disable_unprepare(ice->core_clk); return 0; } @@ -780,8 +797,13 @@ static const struct dev_pm_ops ice_pm_ops = { SET_RUNTIME_PM_OPS(ice_runtime_suspend, ice_runtime_resume, NULL) }; +static const struct engine_desc cfg_fw_managed = { + .fw_managed = true, +}; + static const struct of_device_id qcom_ice_of_match_table[] = { { .compatible = "qcom,inline-crypto-engine" }, + { .compatible = "qcom,sa8255p-inline-crypto-engine", .data = &cfg_fw_managed }, { }, }; MODULE_DEVICE_TABLE(of, qcom_ice_of_match_table); -- 2.34.1