From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B77CA40F8C7 for ; Fri, 8 May 2026 21:23:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778275424; cv=none; b=XLN0Q8Gjb95yBP0Qu0gXemXJ8+bgtrnPlb+LD7G/RmhwEOK8bz/vI9dVyA1acZdzthQakAxsowfQDhwLcFNk504uzwVRPBesfc0oH989luKFhHZz/0S9d2fiQzfw+OkvNeDRARhw/ijRgVTSjhKgsZ0lpo4dzgAIBoob188Bhlw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778275424; c=relaxed/simple; bh=7AVn6choG9U1fLKMAnVSJ1zfVNTIb/y7AKxs+8P5jUA=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=KyFP7E4wxgf0wtVgzJKf6xZBEofwhGXiwGYj9KOGI70C7mgXmO0o6w0Mpcx28ncPT5h1LZbaYbS79EWIw0NTQ2zInu+lRHOtSS/6+S4t6DoHyc71R5GlX2+Ful+tOxay+qmmZRtP/p6U2n2p4UeSFyJhWLsldSH1hGvBFwvzrbg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=QtlXwfYW; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=BWBfHBpV; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="QtlXwfYW"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="BWBfHBpV" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 648G55Eh1116855 for ; Fri, 8 May 2026 21:23:42 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:message-id:mime-version :subject:to; s=qcppdkim1; bh=PlbMjBqGuJdYSGZkU4MUuEB+aZERXuCnNc/ qXM66qQY=; b=QtlXwfYWM7+kz54uH0JcGtsMF0t3FZyRYSgq/6H++zDD51S2g+P enSb70kvKijhnz9MvhXsqvcACkwJ0DIc2utAKbqWyJwMF85CXY7X3vafZFweAJ1V 6xCyRdEeh1KLs6G34MHF2RJjTjcGllFkuniTvfY4p4ftjhnQzaISy6oluKiuaxOr u+ZjR2oA5K2R6+cHDMxirudnGmGjgPJ39qHmabTQVYXVdkv8Im+AQjvjTaZq4c6f CInbP349r/xm0xnfDprxKo4Nj+n+LEEw5oNC1zO1lvHIBcwGBp+44UV1PPpxnS6P /QD+xzIAH5vmVtQPBp0WMYojCEEi0O1sf8g== Received: from mail-dy1-f199.google.com (mail-dy1-f199.google.com [74.125.82.199]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4e1k1ph06n-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 08 May 2026 21:23:41 +0000 (GMT) Received: by mail-dy1-f199.google.com with SMTP id 5a478bee46e88-2ef37c3f773so2878504eec.1 for ; Fri, 08 May 2026 14:23:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1778275421; x=1778880221; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=PlbMjBqGuJdYSGZkU4MUuEB+aZERXuCnNc/qXM66qQY=; b=BWBfHBpVcb7AH0mXe6Z+yW+lyDc8RVBD2VFkKb/L4jLe7rnlPGpKgPrcsI1HGbjybi 7nEkU6AOj5XmxAN/OA72WgmUHQ1Nrp/7ilyR/WJ0crco+0Q1lScl8uqaYwURKoVbb54D CTQ3Zatw7ONVnULNAEa6yKd3XlX+jy/gPb8INdvEzO+sA9KAo8Qjsqopg+32yUoDup7b gETuSww0DNQseUatdZyraW17l3ThxnXb8J0qhDiFZswJnT3kmGZZy6TOOJntwrZDS75D HGqv3DMx4AaTJARQmk2NI+r7k0Eo3W8dKFUjO7pA9fZFbD6h/CowkdIMR6iJjOtab9Fq QJ5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778275421; x=1778880221; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=PlbMjBqGuJdYSGZkU4MUuEB+aZERXuCnNc/qXM66qQY=; b=k3PDcGL3E9TiNSZZIA6e7y1Mt4LFDOfKe5e4MFarampqYinZKlOaiPgjtKEYt/g5js xcqo0ChBXIJqZ0xaAJFJc97L1qto2k/uIvjDyMiydLgE0n5WTgq9++MSkC3Ued8Dtk2h 8lIPzrr0R2ba2hAGHgNPdXDr0R9OcVYg6QhCQu/P98g/syj5J9OQBWF6vQ3r/yr9l9h2 daqEYcidDmgaFmiYGQHJ4LcGUoWSx3BnpkL0EedAn07NjAm094OOqrtGBNbAGebEed2f 3Ko7KS2u0xAH7QNKdhGq8L8Wwz6i/0CrqadxigOjB4UwatwYoDfDmuyAHeK/BHt9gdFO ApTw== X-Gm-Message-State: AOJu0YyOXNUgsZXaBvKciwY/2MnCTAs+t/Y1MICVWt9tiX11LX6oHTgV XhTkMCZeOa4OlwewEnlhAtxVPJy4fV6Bv1EDKplq7iy7jP7ICV8om+odJSC1j3KXttdN+G9SSkY MChWgRyf2zt2QaTQjKmjf5TgFxVJehf7CLr4uRCxmuh/9iVt9XEVGAKKV3o2QsVd5mOPYLRZVnX c= X-Gm-Gg: Acq92OGP/5xV4fDeTiKmVM8oa9ukNpdTt+mE5kb8+EHx0SxXGaCh/h5NEgXwCAhzR2x 6DZMvazrzbwbet/MuqqdKi5AkPaCGLPFui7GBmLuuxX0IGsgiuEfddExd49w434qhT+w5tg94DQ z/oozAXbwQ3r96cFVe0KSLz3ceUK/Uk0zLosdqJZ0zfAfx21tTkfUo3kpcxD5gw5BflX4vqjwEQ QPKJsipp1qp+csaVVa+52l/23BHdE8fcZFxfrgqKCz5hALasVM6BiL1WefV8H7IK9VsXBrsRZKG 7cJeL06Pfa+6RLXs1KDD6ZRWQ1yztNqNA1CCE9J8XF7HzPy6XtiRpH5Bj7ru80h4SEi4bzUnp5j sK9lM4C5HyOa+kAb0GXtn6MREYoLETd4= X-Received: by 2002:a05:7300:2216:b0:2c5:220c:5670 with SMTP id 5a478bee46e88-2f5482663b5mr7637744eec.2.1778275421275; Fri, 08 May 2026 14:23:41 -0700 (PDT) X-Received: by 2002:a05:7300:2216:b0:2c5:220c:5670 with SMTP id 5a478bee46e88-2f5482663b5mr7637721eec.2.1778275420681; Fri, 08 May 2026 14:23:40 -0700 (PDT) Received: from localhost ([140.82.166.162]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-2f8859eb4b7sm4075754eec.2.2026.05.08.14.23.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 May 2026 14:23:40 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tjeznach@rivosinc.com, joro@8bytes.org, will@kernel.org, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org Subject: [PATCH 0/2] iommu/riscv: Enable IOMMU_DMA Date: Fri, 8 May 2026 16:23:37 -0500 Message-ID: <20260508212339.381933-1-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: 2AyXXaDy18mhulZfAidxAj-HlWTf-jE9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA4MDIxMSBTYWx0ZWRfX1BlCEnIwnYvg puzAFFtrDOLu2aBp2i9v9Xf2/s3RCeTTysw9LXlMB978yVCDWi66OEkJzMpx5n8F8ExFvcy+fHR rocNu5orzVlcIgWb8C7dGAl5FvmEk2IOwBRwn9PfEcbdegyXceGP2Uv4XzUp4xHpL20U5bcJprY q4jtJY5Ujcq7KHu6qj3t3YeXheQTAcgzw2SSRJVw+G7TwwyK5yQTlhkVypKPRKtNX8i3fr2p53r ZcsnByb46lIyTT6zG+LVNI+MGzJFJvk2NGmcSvpOPHod+x1XMjx3Lpc7rhv2Dx4ISC1Woo8TH1A Q564qTDFnG5y9dq8k7281sfrDzZDoNnXpNOnqE+pvcBg6Yv5OxyLXQYOW/SSCBEuAkLutblh2z+ 8oKDxSdjKaRbOaIKqhhyGSdR7BQbnYB6ImwgMaw3X1BWgapYDnGjpw/I0YAceEh+yhydClBYd7M ktCgOiCDDG8pzi0/hrw== X-Authority-Analysis: v=2.4 cv=COwamxrD c=1 sm=1 tr=0 ts=69fe545d cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=cvcws7F5//HeuvjG1O1erQ==:17 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=vm3i78yGLUWP3Dov9wMA:9 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-ORIG-GUID: 2AyXXaDy18mhulZfAidxAj-HlWTf-jE9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-07_02,2026-05-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 spamscore=0 phishscore=0 suspectscore=0 malwarescore=0 impostorscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605080211 Arguably long overdue, let's start using paging domains. One blocker to enabling IOMMU_DMA was that platforms with IMSICs would fault on MSIs - Patch1 handles that. And, since QEMU is still one of the most- used riscv platforms, another issue is that commit 69541898b71a ("iommu/riscv: Enable SVNAPOT support for contiguous ptes") exposes a bug in the QEMU RISC-V IOMMU model. A patch for that is now on the QEMU list[1]. Rest assured that the irqbypass work will get a v3 posted soon. This series can be independently merged though since we don't need irqbypass to enable paging domains and deliver MSIs for host devices. [1] https://lore.kernel.org/all/20260508205129.377032-1-andrew.jones@oss.qualcomm.com/ Andrew Jones (1): iommu/riscv: Map IMSIC addresses for paging domains Tomasz Jeznach (1): iommu/dma: enable IOMMU_DMA for RISC-V drivers/iommu/Kconfig | 2 +- drivers/iommu/riscv/iommu.c | 34 +++++++++++++++++++++++++++++ include/linux/irqchip/riscv-imsic.h | 7 ++++++ 3 files changed, 42 insertions(+), 1 deletion(-) -- 2.43.0