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Fri, 08 May 2026 14:23:42 -0700 (PDT) X-Received: by 2002:a05:7022:ead2:b0:128:ca83:5aa3 with SMTP id a92af1059eb24-131967d7ba7mr7777486c88.1.1778275422371; Fri, 08 May 2026 14:23:42 -0700 (PDT) Received: from localhost ([140.82.166.162]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1327865700asm3984668c88.9.2026.05.08.14.23.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 May 2026 14:23:42 -0700 (PDT) From: Andrew Jones To: linux-riscv@lists.infradead.org, iommu@lists.linux.dev Cc: linux-kernel@vger.kernel.org, tjeznach@rivosinc.com, joro@8bytes.org, will@kernel.org, pjw@kernel.org, palmer@dabbelt.com, anup@brainfault.org Subject: [PATCH 1/2] iommu/riscv: Map IMSIC addresses for paging domains Date: Fri, 8 May 2026 16:23:38 -0500 Message-ID: <20260508212339.381933-2-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260508212339.381933-1-andrew.jones@oss.qualcomm.com> References: <20260508212339.381933-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=DaEnbPtW c=1 sm=1 tr=0 ts=69fe545f cx=c_pps a=bS7HVuBVfinNPG3f6cIo3Q==:117 a=cvcws7F5//HeuvjG1O1erQ==:17 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=5LAesA1oWso2HGznwIcA:9 a=vBUdepa8ALXHeOFLBtFW:22 X-Proofpoint-GUID: lkvat569m458UgVbMT7qRX_4yOuPXGOX X-Proofpoint-ORIG-GUID: lkvat569m458UgVbMT7qRX_4yOuPXGOX X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA4MDIxMSBTYWx0ZWRfX4rIMpgQ08L1T Npg/PFzqQKkmml9TCNTOY0KFsrZS0c6kejw5a5JeqAG0ddWbYboAsA9GA1Esk9YuNVV525RFMvV +qOqsBipGpS5/MulMr8RoLscIvVFoY/vhfNdx6D2+8oNb1FWKtPNdS7pT05mJZ2C2+gicsSCJ4Y Ddf+TNDvzRKkbH/9HyliLB2fsEj2290jphA2fSTs6JTGYurf738whOBuipk7/FuUSYowbrGI5yt 1MiEmrhf940znjJF1Y3MeuRQYj6Sduf9ujEAOUlMJBL9aC46Cr/v73e36pX85kfP+goGAG1Vzg/ H7IKnwtwu894bDSGHcy5iCthsIHLdkc1jm7A1RA8g5XhR9/3vxfduPq7bgPcreOVxTFtvrLNM99 fIQ6yrAfsc9F/E/FYBQEn5kLh0agl5DkqQ1Lh3BMag8a7AASCbR6wAWewJILUi3H7k0e9k0UKp9 i+BP0i/QY4rDlu65eHA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-07_02,2026-05-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 spamscore=0 priorityscore=1501 adultscore=0 malwarescore=0 suspectscore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605080211 When IOMMU_DMA is enabled, devices get paging domains and MSI writes to IMSIC interrupt files must be handled correctly in the s-stage. As the device always writes to the host physical IMSIC addresses, which the IMSIC irqchip programs directly, install s-stage identity mappings for the host IMSICs. But, use IOMMU_RESV_DIRECT_RELAXABLE since the 1:1 mappings aren't required for device assignment. Loop over the cpus rather than imsic groups to handle asymmetric configurations. Signed-off-by: Andrew Jones --- drivers/iommu/riscv/iommu.c | 34 +++++++++++++++++++++++++++++ include/linux/irqchip/riscv-imsic.h | 7 ++++++ 2 files changed, 41 insertions(+) diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c index a31f50bbad35..3c6aa9d69f95 100644 --- a/drivers/iommu/riscv/iommu.c +++ b/drivers/iommu/riscv/iommu.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -1286,6 +1287,38 @@ static struct iommu_domain *riscv_iommu_alloc_paging_domain(struct device *dev) return &domain->domain; } +static void riscv_iommu_get_resv_regions(struct device *dev, struct list_head *head) +{ + const struct imsic_global_config *imsic_global; + unsigned int cpu; + + if (!imsic_enabled()) + return; + + imsic_global = imsic_get_global_config(); + + for_each_possible_cpu(cpu) { + const struct imsic_local_config *local; + struct iommu_resv_region *reg; + + local = per_cpu_ptr(imsic_global->local, cpu); + if (!local->msi_va) + continue; + + /* + * The device always writes to the host physical IMSIC address, so install + * identity mappings directly. Use IOMMU_RESV_DIRECT_RELAXABLE instead of + * IOMMU_RESV_DIRECT since these 1:1 mappings are not required for assigned + * devices. + */ + reg = iommu_alloc_resv_region(local->msi_pa, IMSIC_MMIO_PAGE_SZ, + IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO, + IOMMU_RESV_DIRECT_RELAXABLE, GFP_KERNEL); + if (reg) + list_add_tail(®->list, head); + } +} + static int riscv_iommu_attach_blocking_domain(struct iommu_domain *iommu_domain, struct device *dev, struct iommu_domain *old) @@ -1401,6 +1434,7 @@ static const struct iommu_ops riscv_iommu_ops = { .blocked_domain = &riscv_iommu_blocking_domain, .release_domain = &riscv_iommu_blocking_domain, .domain_alloc_paging = riscv_iommu_alloc_paging_domain, + .get_resv_regions = riscv_iommu_get_resv_regions, .device_group = riscv_iommu_device_group, .probe_device = riscv_iommu_probe_device, .release_device = riscv_iommu_release_device, diff --git a/include/linux/irqchip/riscv-imsic.h b/include/linux/irqchip/riscv-imsic.h index 4b348836de7a..ba3000f047b0 100644 --- a/include/linux/irqchip/riscv-imsic.h +++ b/include/linux/irqchip/riscv-imsic.h @@ -88,6 +88,13 @@ static inline const struct imsic_global_config *imsic_get_global_config(void) #endif +static inline bool imsic_enabled(void) +{ + const struct imsic_global_config *imsic_global = imsic_get_global_config(); + + return imsic_global && imsic_global->nr_ids; +} + #if IS_ENABLED(CONFIG_ACPI) && IS_ENABLED(CONFIG_RISCV_IMSIC) int imsic_platform_acpi_probe(struct fwnode_handle *fwnode); struct fwnode_handle *imsic_acpi_get_fwnode(struct device *dev); -- 2.43.0