From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BEC9F43E9CD for ; Mon, 11 May 2026 18:21:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778523684; cv=none; b=X5sra4IB7gEYmJd/QRxR4bZ8VcW/0stv7PruGV0rC80zpuYUipbmscxuHd0E6MCOrBQmQi1Ovfn1mWSoWX/vH+0s8gw3QmfBbC4Vl8mhwT2zeNw27LdboYvEgHEOU10YleFXsgLpj5a/zHnW7DnySpiM8vrL2qN9i8JJVjnKp4s= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778523684; c=relaxed/simple; bh=QlHRn1HXjDNwINNOyiiCfFBAmz9XFP0jXQyyV/BKpzg=; h=From:Subject:Date:Message-Id:MIME-Version:Content-Type:To:Cc; b=PXzCQOc0NYMAxlwn6TM5zvMubccRxkTiIdeJsJy/g0GXfxn6KDb7FsI+TaiQKVmi8mmsMTm5b7j+3NFkbice9Q6SXwwyOMiopi809BN6U5kwS6I8WPP496CBe3YAFFNnAFl9s9KRJN+wtFK1NDWGd1jp9N4utRbRRQ+eR14fgo8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=cXeKiJmf; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="cXeKiJmf" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1778523680; bh=QlHRn1HXjDNwINNOyiiCfFBAmz9XFP0jXQyyV/BKpzg=; h=From:Subject:Date:To:Cc:From; b=cXeKiJmfuduU4ZQDt2mRglV28CEYSQoUK5XGrSOc8JAkoWg+OlDJaff8fz7QbSQHE J8/G1NzfY+NbM31r21oFgCjaYWcx36pVYyzXlV2oDVtF2ay6aXYyzBlArIm6EJiaky 9z6YNBrkL6XxYlJwRmHNouQovV5GugsmpgTAJBmOPV1kKwJFuVzH/g9Jxg3Me3dwkK wIH1rW/8l3cECNMud2F4mYRfSfffO24w7RffJ/gSmUG2gruPJGxSQ5VhcpCOx0jNA9 TrlvMUMZXa0xQ8K1N2MFgQwJXcppRLNygv/OEGYhK1FoZ/8lk9Z6emunWdDgJvssiq XyLsbsBToXG4Q== Received: from localhost (unknown [100.64.0.241]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with ESMTPSA id 9240F17E05FC; Mon, 11 May 2026 20:21:20 +0200 (CEST) From: Cristian Ciocaltea Subject: [PATCH v2 0/6] phy: rockchip: samsung-hdptx: Clock fixes and API transition cleanups Date: Mon, 11 May 2026 21:21:14 +0300 Message-Id: <20260511-hdptx-clk-fixes-v2-0-664e41379cab@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAAAAAAAC/3WNyw7CIBREf6W5a6+h1wZaV/6H6QJ5CLGWBhpS0 /DvYvcuz0zOzA7JRG8SXJsdosk++TBXoFMDysn5adDrykCMOCMS6PSybqimF1q/mYSd6IjzC9m eE1RrieYoqnQfKzuf1hA/x0Fuf+n/rdwiQzsMvSXBSTN7U2Ga5CNEeVbhDWMp5QscxNdasgAAA A== X-Change-ID: 20260227-hdptx-clk-fixes-47426632f862 To: Vinod Koul , Neil Armstrong , Heiko Stuebner , Algea Cao , Dmitry Baryshkov Cc: kernel@collabora.com, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?q?Thomas_Niederpr=C3=BCm?= , Simon Wright X-Mailer: b4 0.15.1 This series provides a set of bug fixes and cleanups for the Rockchip Samsung HDPTX PHY driver. The first part of the series (i.e. PATCH 1 & 2) addresses clock rate calculation and synchronization issues. Specifically, it fixes edge cases where the PHY PLL is pre-programmed by an external component (like a bootloader) or when changing the color depth (bpc) while keeping the modeline constant. Because the Common Clock Framework .set_rate() callback might not be invoked if the pixel clock remains unchanged, this previously led to out-of-sync states between CCF and the actual HDMI PHY configuration. The second part focuses on code cleanups and modernizing the register access. Now that dw_hdmi_qp driver has fully switched to using phy_configure(), we can drop the deprecated TMDS rate setup workarounds and the restrict_rate_change flag logic. Finally, it refactors the driver to consistently use standard bitfield macros. Signed-off-by: Cristian Ciocaltea --- Changes in v2: - Collected Tested-by tags from Thomas and Simon - Fixed a typo in commit description of patch 1 - Added a comment in patch 2 explaining why PLL config errors are ignored for rk_hdptx_phy_consumer_get() - Added a missed FIELD_GET conversion for lcpll_hw.pms_sdiv in patch 6 - Rebased onto latest phy/fixes - Link to v1: https://lore.kernel.org/r/20260227-hdptx-clk-fixes-v1-0-f998f2762d0f@collabora.com --- Cristian Ciocaltea (6): phy: rockchip: samsung-hdptx: Fix rate recalculation for high bpc phy: rockchip: samsung-hdptx: Handle uncommitted PHY config changes phy: rockchip: samsung-hdptx: Drop TMDS rate setup workaround phy: rockchip: samsung-hdptx: Drop restrict_rate_change handling phy: rockchip: samsung-hdptx: Simplify GRF access with FIELD_PREP_WM16() phy: rockchip: samsung-hdptx: Consistently use bitfield macros drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 216 ++++++++++------------ 1 file changed, 95 insertions(+), 121 deletions(-) --- base-commit: a4058c09dd6e28ec33316fd6eb45ddae4cab1f31 change-id: 20260227-hdptx-clk-fixes-47426632f862