From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 757EB25B085 for ; Wed, 13 May 2026 04:47:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778647664; cv=none; b=bCH+DIOc9RiAh66/sjYqv3ZTV0Bi+5NiQCvCV7jQDzGDmfvh1incFN7ympqzsISs0GTmYYb0ETtLIG9hhfXLUAVjDEVpdvqFsyXhCmjgQW2dcx/BI3nwVHwr2UfUQ7r/79XHohqzLDZ4FSaUrFt2//goG/+L5I10gV48d3uUGz0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778647664; c=relaxed/simple; bh=TmCvO12iAjHSRBJDFbEkaVzXDT8a8vX3wzPeUnlsa9s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=D88lYwK3TK6DoKxPkle99o0f6P8BoLn51Tl4cVPwywk3SA2WI8y3FAL9nVvg30AGOX5zMqp2BUmCYT0Xc0iRJRcW8ZGaBrFuOfOvsKkLjvPYfc3DBHIYH01qs28CnGX1dBYw/+b8K9if6X5h6L7rPosIqpjzxt21hpzr4Le8gUU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=sIw08p51; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="sIw08p51" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 82B061595; Tue, 12 May 2026 21:47:36 -0700 (PDT) Received: from a085714.blr.arm.com (a085714.arm.com [10.164.18.87]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 305A53F905; Tue, 12 May 2026 21:47:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1778647661; bh=TmCvO12iAjHSRBJDFbEkaVzXDT8a8vX3wzPeUnlsa9s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=sIw08p51XIj5EbAwuNGYLYUlpNL2nf3nisSDjSd6CTG5MqAQE3CPjzFwXRo9Tctza dmq1pAKdWQqtprsnDuwV8WLy9TcNI3EPXi6eprgKVZtL1goOwG6DhSoroM/thdRCZg gm/DV38U6ihb2/WizMSYIpahGPpI3K55FfOqXhaQ= From: Anshuman Khandual To: linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Ryan Roberts , Mark Rutland , Lorenzo Stoakes , Andrew Morton , David Hildenbrand , Mike Rapoport , Linu Cherian , Usama Arif , linux-kernel@vger.kernel.org, linux-mm@kvack.org Subject: [RFC V2 13/14] arm64/mm: Add an abstraction level for tlbi_op Date: Wed, 13 May 2026 10:15:46 +0530 Message-ID: <20260513044547.4128549-14-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260513044547.4128549-1-anshuman.khandual@arm.com> References: <20260513044547.4128549-1-anshuman.khandual@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Linu Cherian With FEAT_D128, a new instruction aka TLBIP is being introduced for the TLB range operations which has an argument size of 128 bit. Add an abstraction level to void (*tlbi_op)(u64 arg) helpers to support the D128 variations when applicable. No functional changes are introduced with this patch. Signed-off-by: Linu Cherian Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/tlbflush.h | 70 ++++++++++++++++--------------- 1 file changed, 37 insertions(+), 33 deletions(-) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index c0bf5b398041..361d74ef8016 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -162,49 +162,53 @@ static inline void sme_dvmsync_batch(struct arch_tlbflush_unmap_batch *batch) #define TLBI_TTL_UNKNOWN INT_MAX -typedef void (*tlbi_op)(u64 arg); +typedef u64 tlbi_args_t; +#define __tlbi_wrapper(op, arg) __tlbi(op, arg) +#define __tlbi_user_wrapper(op, arg) __tlbi_user(op, arg) -static __always_inline void vae1is(u64 arg) +typedef void (*tlbi_op)(tlbi_args_t arg); + +static __always_inline void vae1is(tlbi_args_t arg) { - __tlbi(vae1is, arg); - __tlbi_user(vae1is, arg); + __tlbi_wrapper(vae1is, arg); + __tlbi_user_wrapper(vae1is, arg); } -static __always_inline void vae2is(u64 arg) +static __always_inline void vae2is(tlbi_args_t arg) { - __tlbi(vae2is, arg); + __tlbi_wrapper(vae2is, arg); } -static __always_inline void vale1(u64 arg) +static __always_inline void vale1(tlbi_args_t arg) { - __tlbi(vale1, arg); - __tlbi_user(vale1, arg); + __tlbi_wrapper(vale1, arg); + __tlbi_user_wrapper(vale1, arg); } -static __always_inline void vale1is(u64 arg) +static __always_inline void vale1is(tlbi_args_t arg) { - __tlbi(vale1is, arg); - __tlbi_user(vale1is, arg); + __tlbi_wrapper(vale1is, arg); + __tlbi_user_wrapper(vale1is, arg); } -static __always_inline void vale2is(u64 arg) +static __always_inline void vale2is(tlbi_args_t arg) { - __tlbi(vale2is, arg); + __tlbi_wrapper(vale2is, arg); } -static __always_inline void vaale1is(u64 arg) +static __always_inline void vaale1is(tlbi_args_t arg) { - __tlbi(vaale1is, arg); + __tlbi_wrapper(vaale1is, arg); } -static __always_inline void ipas2e1(u64 arg) +static __always_inline void ipas2e1(tlbi_args_t arg) { - __tlbi(ipas2e1, arg); + __tlbi_wrapper(ipas2e1, arg); } -static __always_inline void ipas2e1is(u64 arg) +static __always_inline void ipas2e1is(tlbi_args_t arg) { - __tlbi(ipas2e1is, arg); + __tlbi_wrapper(ipas2e1is, arg); } static __always_inline void __tlbi_level_asid(tlbi_op op, u64 addr, u32 level, @@ -475,32 +479,32 @@ static inline void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) * operations can only span an even number of pages. We save this for last to * ensure 64KB start alignment is maintained for the LPA2 case. */ -static __always_inline void rvae1is(u64 arg) +static __always_inline void rvae1is(tlbi_args_t arg) { - __tlbi(rvae1is, arg); - __tlbi_user(rvae1is, arg); + __tlbi_wrapper(rvae1is, arg); + __tlbi_user_wrapper(rvae1is, arg); } -static __always_inline void rvale1(u64 arg) +static __always_inline void rvale1(tlbi_args_t arg) { - __tlbi(rvale1, arg); - __tlbi_user(rvale1, arg); + __tlbi_wrapper(rvale1, arg); + __tlbi_user_wrapper(rvale1, arg); } -static __always_inline void rvale1is(u64 arg) +static __always_inline void rvale1is(tlbi_args_t arg) { - __tlbi(rvale1is, arg); - __tlbi_user(rvale1is, arg); + __tlbi_wrapper(rvale1is, arg); + __tlbi_user_wrapper(rvale1is, arg); } -static __always_inline void rvaale1is(u64 arg) +static __always_inline void rvaale1is(tlbi_args_t arg) { - __tlbi(rvaale1is, arg); + __tlbi_wrapper(rvaale1is, arg); } -static __always_inline void ripas2e1is(u64 arg) +static __always_inline void ripas2e1is(tlbi_args_t arg) { - __tlbi(ripas2e1is, arg); + __tlbi_wrapper(ripas2e1is, arg); } static __always_inline void __tlbi_range(tlbi_op op, u64 addr, -- 2.43.0