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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Vzi6GOrLjvk/PiF8s2tXh4BJz45DOeEU1t+60OZcE7TcUSf49esjf4G6NArwp9gXE8roCp7geoFpuBrxPZ7kgft1HByiTIynPByae5xHfa4D/9WYzHp7eVWx3PfQkSZBPS8C2i8Sxf8C24rucxQ4HH2MOLihi0NxHHHm4p7C8Vh/4cpZ8502vgAlILwkJhM5bZaWdHk2iKyc/BEHJDVChWjRVOLe0OoBa0Kb6gRsTnKxGmSo9O3cTPhLmJh3mXTt7HqPapBoYyfsInTLgO/FV0Gbq6ptx31ErB9u5KdybrH2sySlyel+KD0Y65oVQPacVgBJXuaPvAO5lc4NH93vpxG2VmZZD5JB+kYYf3exN/DJ7aXU89G/Bxsjwx3zpVSpPkvvsXuXVQ8BtN8DVFoOjoY/HB0prsVm+l0dPEZUpsownIc8l7qts/hIqGZpyLFu X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 May 2026 15:12:41.0506 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 82ec0c2d-3b00-4e86-5c0e-08deb426bd5b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075ED.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5946 Define the UAPI structures hsmp_metric_table_zen6_iod, hsmp_metric_table_zen6_ccd and the top-level hsmp_metric_table_zen6 to describe the per-IOD and per-CCD metrics layout for AMD Family 1Ah Model 50h-5Fh processors (HSMP protocol version 7). These structures allow userspace tools to interpret the raw metric table binary exposed through the HSMP character device. Driver enablement for protocol version 7 is added in a follow-up patch. Reviewed-by: Suma Hegde Co-developed-by: Muthusamy Ramalingam Signed-off-by: Muthusamy Ramalingam Signed-off-by: Muralidhara M K --- Changes: v1->v2: Split the change v2->v3: Move proto version check to seperate patch arch/x86/include/uapi/asm/amd_hsmp.h | 88 ++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/arch/x86/include/uapi/asm/amd_hsmp.h b/arch/x86/include/uapi/asm/amd_hsmp.h index 603d62f8d4da..da3e3bbfa33e 100644 --- a/arch/x86/include/uapi/asm/amd_hsmp.h +++ b/arch/x86/include/uapi/asm/amd_hsmp.h @@ -575,6 +575,94 @@ struct hsmp_metric_table { __u32 gfxclk_frequency[8]; }; +#define F1A_M50_M5F_MAX_CORES_PER_CCD_32 32 +#define F1A_M50_M5F_MAX_FREQ_TABLE_SIZE 4 +#define F1A_M50_M5F_MAX_XGMI 8 +#define F1A_M50_M5F_MAX_PCIE 8 +#define F1A_M50_M5F_MAX_CCD 8 + +/* Metrics table (supported only with proto version 7) */ +struct hsmp_metric_table_zen6_iod { + __u32 num_active_ccds; + __u32 accumulation_counter; + + /* TEMPERATURE */ + __u64 max_socket_temperature_acc; + + /* POWER */ + __u32 socket_power_limit; + __u32 max_socket_power_limit; + __u64 socket_power_acc; + __u64 core_power_acc; + __u64 uncore_power_acc; + + /* ENERGY */ + __u64 timestamp; + __u64 socket_energy_acc; + __u64 core_energy_acc; + __u64 uncore_energy_acc; + + /* FREQUENCY */ + __u64 fclk_frequency_acc; + __u64 uclk_frequency_acc; + __u64 ddr_rate_acc; + __u64 lclk_frequency_acc[F1A_M50_M5F_MAX_FREQ_TABLE_SIZE]; + + /* FREQUENCY RANGE */ + __u32 fclk_frequency_table[F1A_M50_M5F_MAX_FREQ_TABLE_SIZE]; + __u32 uclk_frequency_table[F1A_M50_M5F_MAX_FREQ_TABLE_SIZE]; + __u32 ddr_rate_table[F1A_M50_M5F_MAX_FREQ_TABLE_SIZE]; + __u32 max_df_pstate_range; + __u32 min_df_pstate_range; + __u32 lclk_frequency_table[F1A_M50_M5F_MAX_FREQ_TABLE_SIZE]; + __u32 max_lclk_dpm_range; + __u32 min_lclk_dpm_range; + + /* XGMI */ + __u64 xgmi_bit_rate[F1A_M50_M5F_MAX_XGMI]; + __u64 xgmi_read_bandwidth[F1A_M50_M5F_MAX_XGMI]; + __u64 xgmi_write_bandwidth[F1A_M50_M5F_MAX_XGMI]; + + /* ACTIVITY */ + __u64 socket_c0_residency_acc; + __u64 socket_df_cstate_residency_acc; + __u64 dram_read_bandwidth_acc; + __u64 dram_write_bandwidth_acc; + __u32 max_dram_bandwidth; + __u64 pcie_bandwidth_acc[F1A_M50_M5F_MAX_PCIE]; + + /* THROTTLERS */ + __u32 prochot_residency_acc; + __u32 ppt_residency_acc; + __u32 thm_residency_acc; + __u32 vrhot_residency_acc; + __u32 cpu_tdc_residency_acc; + __u32 soc_tdc_residency_acc; + __u32 io_mem_tdc_residency_acc; + __u32 fit_residency_acc; +}; + +struct hsmp_metric_table_zen6_ccd { + __u32 core_apicid_of_thread0[F1A_M50_M5F_MAX_CORES_PER_CCD_32]; + __u64 core_c0[F1A_M50_M5F_MAX_CORES_PER_CCD_32]; + __u64 core_cc1[F1A_M50_M5F_MAX_CORES_PER_CCD_32]; + __u64 core_cc6[F1A_M50_M5F_MAX_CORES_PER_CCD_32]; + __u64 core_frequency[F1A_M50_M5F_MAX_CORES_PER_CCD_32]; + __u64 core_frequency_effective[F1A_M50_M5F_MAX_CORES_PER_CCD_32]; + __u64 core_power[F1A_M50_M5F_MAX_CORES_PER_CCD_32]; +}; + +/* + * Metrics table for Family 0x1A, Models 0x50 to 0x5F, table version 0x00700000 + * + * Future processors within the same family and model may support a + * variable number of CCDs and cores + */ +struct hsmp_metric_table_zen6 { + struct hsmp_metric_table_zen6_iod iod; + struct hsmp_metric_table_zen6_ccd ccd[F1A_M50_M5F_MAX_CCD]; +}; + /* Reset to default packing */ #pragma pack() -- 2.34.1