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[85.4.92.72]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-45da15a562dsm32845129f8f.33.2026.05.17.16.41.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 May 2026 16:41:27 -0700 (PDT) From: Alexander Sverdlin To: linux-sunxi@lists.linux.dev Cc: Alexander Sverdlin , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Andre Przywara , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 4/5] arm64: dts: allwinner: A133: add support for Baijie Helper A133 board Date: Mon, 18 May 2026 01:41:30 +0200 Message-ID: <20260517234134.2737320-5-alexander.sverdlin@gmail.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260517234134.2737320-1-alexander.sverdlin@gmail.com> References: <20260517234134.2737320-1-alexander.sverdlin@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Baijie Helper A133 board is a development board around Baijie A133 Core SBC. Features: - 1/2/4GiB LPDDR4 DRAM - 8/16/32GiB eMMC - AXP707 PMIC - USB-C OTG port in peripheral mode (via onboard hub) - 2 USB 2.0 ports - MicroSD slot and on-board eMMC module - Gigabit Ethernet - Bluetooth - WiFi Add initial support for both the Helper and Core boards, including UART, PMU, eMMC, USB, Ethernet, LRADC-connected buttons. UART1 can only be used for Bluetooth module, but BT-WiFi combo Allwinner AW869A chip has not mainline driver currently. Signed-off-by: Alexander Sverdlin --- Changelog: v3: - added my copyrights into the newly introduced DTs - all DT nodes sorted alphabetically - all always-on regulators commented/propetly named - all regulators got proper voltages (not default ranges) - ADC-sensed buttons K1..K5 added - re-labelled "eth_phy" -> "rgmii_phy" - usbphy 0 switched from host into peripheral mode (downstream from an onboard hub) - typo sun50i-a133-baije-core.dtsi -> sun50i-a133-baijie-core.dtsi v2: - introduced baijie,helper-a133-core compatible for the Core (SoM) board arch/arm64/boot/dts/allwinner/Makefile | 1 + .../allwinner/sun50i-a133-baijie-core.dtsi | 190 ++++++++++++++++++ .../allwinner/sun50i-a133-baijie-helper.dts | 133 ++++++++++++ 3 files changed, 324 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a133-baijie-core.dtsi create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-a133-baijie-helper.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile index d116864b6c2b..926dfa851100 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -18,6 +18,7 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-sopine-baseboard.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-teres-i.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h64-remix-mini-pc.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a100-allwinner-perf1.dtb +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a133-baijie-helper.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a133-liontron-h-a133l.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus.dtb dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-bananapi-m2-plus-v1.2.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a133-baijie-core.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a133-baijie-core.dtsi new file mode 100644 index 000000000000..7a09a5181c03 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-a133-baijie-core.dtsi @@ -0,0 +1,190 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Arm Ltd. + * Copyright (c) 2026 Alexander Sverdlin + */ + +/dts-v1/; + +#include "sun50i-a100.dtsi" +#include "sun50i-a100-cpu-opp.dtsi" + +/{ + compatible = "baijie,helper-a133-core", + "allwinner,sun50i-a100"; + + aliases { + serial1 = &uart1; /* BT module */ + }; +}; + +&cpu0 { + cpu-supply = <®_dcdc2>; +}; + +&lradc { + vref-supply = <®_aldo1>; +}; + +&mmc2 { + vmmc-supply = <®_dcdc1>; + vqmmc-supply = <®_eldo1>; + cap-mmc-hw-reset; + non-removable; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + status = "okay"; +}; + +&pio { + vcc-pb-supply = <®_dcdc1>; + vcc-pc-supply = <®_eldo1>; + vcc-pd-supply = <®_dcdc1>; + vcc-pe-supply = <®_dldo2>; + vcc-pf-supply = <®_dcdc1>; + vcc-pg-supply = <®_dldo1>; + vcc-ph-supply = <®_dcdc1>; + /* + * PL0/PL1 are the I2C connection to PMIC, but it would create a + * circular dependency: + * vcc-pl-supply = <®_aldo3>; + */ +}; + +&r_i2c0 { + status = "okay"; + + axp803: pmic@34 { + compatible = "x-powers,axp803"; + reg = <0x34>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +#include "axp803.dtsi" + +&ac_power_supply { + status = "okay"; +}; + +®_aldo1 { + /* PLL + LRADC analog reference */ + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-pll"; +}; + +®_aldo2 { + /* LPDDR */ + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vdd18-lpddr"; +}; + +®_aldo3 { + /* + * Port L, but linking it to &pio node would create a circular + * dependency because of PL0/PL1 I2C connection to PMIC + */ + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <1000>; + regulator-name = "vcc-pl"; +}; + +®_dcdc1 { + /* Besides Port D it also powers analog part of USB IP and SoC I/O */ + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; +}; + +®_dcdc2 { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd-cpu"; +}; + +®_dcdc3 { + /* CPU core voltage feedback rail */ + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vdd-cpufb"; +}; + +®_dcdc4 { + /* Digital part of USB IP, "System" SoC power rail */ + regulator-always-on; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <950000>; + regulator-name = "vdd-sys"; +}; + +®_dcdc5 { + regulator-always-on; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1500000>; + regulator-name = "vcc-dram"; +}; + +/* DCDC6 unused */ + +®_dldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <1000>; + regulator-name = "vcc-pg"; +}; + +®_dldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <1000>; + regulator-name = "vcc-pe"; +}; + +®_dldo3 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <1000>; + regulator-name = "avdd-csi"; +}; + +®_dldo4 { + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-enable-ramp-delay = <1000>; + regulator-name = "afvcc-csi"; +}; + +®_eldo1 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-enable-ramp-delay = <1000>; + regulator-name = "vcc-pc"; +}; + +®_eldo2 { + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-enable-ramp-delay = <1000>; + regulator-name = "dvdd-csi"; +}; + +/* ELDO3 unused */ + +®_fldo1 { + /* CPUS power rail */ + regulator-always-on; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-name = "vdd-cpus"; +}; diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a133-baijie-helper.dts b/arch/arm64/boot/dts/allwinner/sun50i-a133-baijie-helper.dts new file mode 100644 index 000000000000..0d192c08a6fe --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-a133-baijie-helper.dts @@ -0,0 +1,133 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2025 Arm Ltd. + * Copyright (c) 2026 Alexander Sverdlin + */ + +/dts-v1/; + +#include "sun50i-a133-baijie-core.dtsi" + +#include +#include +#include + +/{ + model = "HelperBoard A133"; + compatible = "baijie,helper-a133", + "baijie,helper-a133-core", + "allwinner,sun50i-a100"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led { + function = LED_FUNCTION_INDICATOR; + color = ; + gpios = <&pio 7 13 GPIO_ACTIVE_LOW>; /* PH13 */ + }; + }; +}; + +&ehci1 { + status = "okay"; +}; + +&emac0 { + pinctrl-names = "default"; + pinctrl-0 = <&rgmii0_pins>; + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + allwinner,rx-delay-ps = <200>; + allwinner,tx-delay-ps = <200>; + status = "okay"; +}; + +&lradc { + wakeup-source; + status = "okay"; + + button-115 { + label = "K1"; + linux,code = ; + channel = <0>; + voltage = <114607>; + }; + + button-235 { + label = "K2"; + linux,code = ; + channel = <0>; + voltage = <234783>; + }; + + button-360 { + label = "K3"; + linux,code = ; + channel = <0>; + voltage = <360000>; + }; + + button-476 { + label = "K4"; + linux,code = ; + channel = <0>; + voltage = <476471>; + }; + + button-592 { + label = "K5"; + linux,code = ; + channel = <0>; + voltage = <591946>; + }; +}; + +&mdio0 { + reset-gpios = <&pio 7 11 GPIO_ACTIVE_LOW>; /* PH11 */ + reset-delay-us = <10000>; + reset-post-delay-us = <150000>; + + rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <1>; + }; +}; + +&mmc0 { + vmmc-supply = <®_dcdc1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + bus-width = <4>; + status = "okay"; +}; + +&ohci1 { + status = "okay"; +}; + +&rgmii0_pins { + drive-strength = <30>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pb_pins>; + status = "okay"; +}; + +&usb_otg { + dr_mode = "peripheral"; + status = "okay"; +}; + +&usbphy { + status = "okay"; +}; -- 2.54.0