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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-302944ffdf0sm16288683eec.8.2026.05.18.22.47.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 22:47:20 -0700 (PDT) From: Qiang Yu Subject: [PATCH RFC v4 0/9] phy: qcom: qmp-pcie: Add link-mode based support for Glymur Gen5x8 PHY Date: Mon, 18 May 2026 22:47:11 -0700 Message-Id: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAF/5C2oC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyTHQUlJIzE vPSU3UzU4B8JSMDIzMDU0ML3ZzMvOz43PyU1Hgg11LX3MDCxNIkOTXVKCVRCaipoCg1LbMCbGC 0UpCbs1IsRLC4NCkrNbkEZBRUWVFqYSnQuhKI2tjaWgCv2FU7jAAAAA== X-Change-ID: 20260518-link_mode_0519-708494cee2da To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio Cc: Qiang Yu , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779169640; l=5263; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=AL+R7tcejSc17oERHvjpfVsvjomjIli7XDrAaoyWxNI=; b=5LnaFyZ6Hj3xMpKJv7wS389amXY+e+6Kx6IAgZS3GGYSuWHXzhVzNoezkYvui4vJNAgjJzQwq oeHvYWlOF8nBkvzRYcmrNY/nk3xOmNlND/MW0ZLUj6Gnoxm7RgyXqll X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Authority-Analysis: v=2.4 cv=VJPtWdPX c=1 sm=1 tr=0 ts=6a0bf96a cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=JfrnYn6hAAAA:8 a=mDV7jF4A4kZc2-CVMwwA:9 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 a=cvBusfyB2V15izCimMoJ:22 a=1CNFftbPRP8L7MoqJWF3:22 X-Proofpoint-ORIG-GUID: S2gruBDX_tWqR-qpBvheyiDd0f2w7MBx X-Proofpoint-GUID: S2gruBDX_tWqR-qpBvheyiDd0f2w7MBx X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDA1MyBTYWx0ZWRfXyghwJGzu10zj mhjwVPgVTPnHD6rBQRSrKeISdMK/4/EJlS+DqLwLktuH5PGyGD2anAJyTjYidZkw3aWIXEkADEI ovbQSCR//CKBOVGU88In82hwIYp50PvMEBpR6QaFgfk+oJD+WkgwcrCG/5x/JZaOEkzmUawfPWK dz+yy7iP5jKHouRZz7sg4pAR8zZnNwqZwhJsm0RP08BMvujF36JQHZrKO0P7fjM7eQDaDIPzcr/ i8Orsh9z1JP3zuP+C92bpVSdTCUtdZ3KYqDk3Rd7oCTIJf0ya0YVHycRwzt+juC5KatAwMjDJC4 GWiXnAT7WVBMzSwOt5EC7CuPY6Pt5RiIQNMSox0Hw3wf8nNH5Ry4WjIfuBQ14uKQyFD5A+gisgU ZqkQQlJbsdMe795AsXRYCJKauxCOsATTlVGAvyuiCpblbu1AzMojHOvZRI/wYiQIfcjbjkfrhyA hm1gcfvlhqOzy1AT7Yw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 adultscore=0 malwarescore=0 bulkscore=0 spamscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190053 Hi all, This RFC proposes a revised model for Glymur Gen5x8 PCIe PHY support. On Glymur, PCIe3 uses one shared Gen5x8 QMP PHY hardware block that can operate in different link topologies (x8 or x4+x4). The previous series approach was not accepted, so this RFC reworks the design to better match the hardware model and DT expectations. This RFC focuses on the link-mode model and associated binding/API changes while keeping prerequisite/independent patches separate. What this RFC changes: - Keep a single PHY provider node for the shared Gen5x8 hardware block. - Select active topology on the provider side via `link-mode`. - Use `#phy-cells = <1>` so consumers can pass logical PHY index to get different phy structure. - Keep legacy (non-link-mode) platforms on the existing path. - Validate mode consistency at probe: - if HW mode matches DT mode, continue; - if mismatch, allow only when selected mode has complete PHY setting tables for all logical PHYs; otherwise fail probe. - Keep programming link-mode register during `power_on`, so DT-selected mode is re-applied when TCSR register may be reset after low-power mode. Mode/cfg selection model: - Introduce mode-indexed match data: - first dimension: `link_mode` - second dimension: `logical_phy_index` - Effective lookup is: cfg = mode_cfgs[active_link_mode].cfgs[logical_phy_index] This allows one shared provider to expose different logical PHY sets per mode. Impact: - Keep existing qmp-pcie PHY operation flow (`phy_ops`) unchanged as much as possible. - Constrain the new design mainly to cfg selection and provider/xlate wiring. - Reuse existing init/power/reset flows with selected cfg, minimizing code churn and behavioral risk. - This RFC is implemented and validated on Glymur Gen5x8, it is designed to be extensible to other multi-mode QMP PCIe PHYs, although additional platform-specific requirements may still be needed. This series depends on a prerequisite patch by Krzysztof Kozlowski: https://lore.kernel.org/r/20260420133616.88740-2-krzysztof.kozlowski@oss.qualcomm.com Thanks, Qiang Signed-off-by: Qiang Yu --- Changes in v4: - Replaced the static bifurcation probe model with a link-mode architecture: the active topology (x8 or x4+x4) is selected via a new "qcom,link-mode" DT property and written to a TCSR register at power-on. This replaces v3 patches 4 and 5 with four new patches (driver refactor, secondary PHY clock/reset lists, link-mode probe infrastructure, and Glymur config). - Updated dt-bindings to describe "qcom,link-mode", #phy-cells = <1>, per-mode validation rules, and added a new header with QMP_PHY_SELECTOR_* and QMP_PCIE_GLYMUR_MODE_* macros. - Patches 2 and 3 (multiple power-domains, multiple nocsr resets) are unchanged from v3. - Link to v3: https://lore.kernel.org/r/20260412-glymur_gen5x8_phy_0413-v3-0-affcebc16b8b@oss.qualcomm.com Changes in v3: - Add description of each power-domain. - Add 64bit prefetchable memory range required by some EPs eg. AI100 ultra. - Move PCIe3a after PCIe3b and move PCIe3a PHY before PCIe3b PHY. - Link to v2: https://lore.kernel.org/all/20260323-glymur_gen5x8_phy_0323-v2-0-ce0fc07f0e52@oss.qualcomm.com/ Changes in v2: - Remove pd_list from qmp_pcie struct as it is not used in phy driver. - align clk-names on " - Link to v1: https://lore.kernel.org/all/20260304-glymur_gen5x8_phy-v1-0-849e9a72e125@oss.qualcomm.com/ To: Vinod Koul To: Neil Armstrong To: Rob Herring To: Krzysztof Kozlowski To: Conor Dooley To: Philipp Zabel To: Bjorn Andersson To: Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org Cc: linux-phy@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org --- Qiang Yu (9): dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add glymur-qmp-gen5x8-pcie-phy compatible dt-bindings: phy: qcom-qmp: Add PHY selector and Glymur link-mode macros phy: qcom: qmp-pcie: Add multiple power-domains support phy: qcom: qmp-pcie: Support multiple nocsr resets phy: qcom: qmp-pcie: Refactor pipe clk register and parse_dt helpers phy: qcom: qmp-pcie: Add clock and reset lists for secondary PHY selector phy: qcom: qmp-pcie: Add link-mode multi-PHY probe infrastructure phy: qcom: qmp-pcie: Add Glymur Gen5x8 PHY config and match data arm64: dts: qcom: glymur: Wire PCIe3a/3b to shared Gen5x8 PHY .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 140 ++++- arch/arm64/boot/dts/qcom/glymur-crd.dtsi | 5 + arch/arm64/boot/dts/qcom/glymur.dtsi | 333 ++++++++++- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 631 ++++++++++++++++++--- include/dt-bindings/phy/phy-qcom-qmp.h | 8 + 5 files changed, 1021 insertions(+), 96 deletions(-) --- base-commit: 4359f733f8edf6be944b9f28ccb6a6c6e9a24aaa change-id: 20260518-link_mode_0519-708494cee2da Best regards, -- Qiang Yu