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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-302944ffdf0sm16288683eec.8.2026.05.18.22.47.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 22:47:21 -0700 (PDT) From: Qiang Yu Date: Mon, 18 May 2026 22:47:12 -0700 Subject: [PATCH RFC v4 1/9] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add glymur-qmp-gen5x8-pcie-phy compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260518-link_mode_0519-v4-1-269cd73cc5d1@oss.qualcomm.com> References: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> In-Reply-To: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio Cc: Qiang Yu , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779169640; l=6963; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=/GzJSMoS9msbAtJPMhiojx/3pCxgRir7RfY8D/ogF4k=; b=KgruVv6cFJ5PFUCqlCf6ohCZdOolIp7KX7leRvFDn+Z3pnbdwhuShekuUrmk8p48yUcIBrD/Z NUUzCxoL1fZB1aKAxH/vkl+NJ4PHcd3fVDuFb7xeQpt+Rt7uohKQgcU X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-GUID: AAMfUJcqToBgnvQmJxNRC8wTYrQImsmI X-Proofpoint-ORIG-GUID: AAMfUJcqToBgnvQmJxNRC8wTYrQImsmI X-Authority-Analysis: v=2.4 cv=BICDalQG c=1 sm=1 tr=0 ts=6a0bf96b cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=3VQrzie0oMwTYjLhUJMA:9 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDA1MyBTYWx0ZWRfXyQJX6U0ky/bg LrQnFWSQxnZRpG4tGwvChBolg2xjLD9NTLI8Sl4JVZ2/H/Wa3MQm16oqQ4I7YCsNYxE6ZqItVT9 1HCryeLOlz6lymFWRqvkcxrNr5Gf5a6/cKMwu4pe9XjeD36OmGydsB/PVjqQ2W99KE+vXe/DVh0 200G1svi0jr8lVaXH3p/CoNyg1fqHIrOvzyvS0Zs5xgmQOUOduA6mRtLgAExlnsX3ACMxNEQBDt 8x4gbd7axhgGIKMc/q/nM2TJGxgxhWkO0mw6wV9g/RXHNsOsiXf2CJbCoC3NBSssOlyp5lP2DZb SqlvHUPEiUi+o3Pn8vKC5pNIVvDxuCNMfjAEvLN4TUPh1ZLSgicW9qFQWui2cTARYG+1DgKaQk3 /KQ4PSrC46uKCCjOz7ZjRUt6hZ5TY3LUOhWJPvx0Jiu3ntVChhBo5HR5rr8PJyRLtJ787PwcfWT rOzbnR4TSdzQ6YUP5+w== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 impostorscore=0 phishscore=0 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190053 The Glymur SoC uses a single PCIe Gen5 PHY hardware block for the PCIe3a/PCIe3b controllers. This block supports two link modes: 1. x4+x4: two 4-lane PHY instances are exposed 2. x8: one 8-lane PHY instance is exposed Add qcom,glymur-qmp-gen5x8-pcie-phy as a multi-mode PHY compatible and document the new link-mode property, which selects the active link mode via a TCSR syscon register. Document the required clocks, resets, and power-domains for both PHY instances active in x8 mode. Use #phy-cells = <1> for this compatible, where the cell value is the PHY index within the active link mode. Signed-off-by: Qiang Yu --- .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 140 ++++++++++++++++++--- 1 file changed, 126 insertions(+), 14 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 3a35120a77ec..5877e40244ba 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -18,6 +18,7 @@ properties: enum: - qcom,glymur-qmp-gen4x2-pcie-phy - qcom,glymur-qmp-gen5x4-pcie-phy + - qcom,glymur-qmp-gen5x8-pcie-phy - qcom,kaanapali-qmp-gen3x2-pcie-phy - qcom,qcs615-qmp-gen3x1-pcie-phy - qcom,qcs8300-qmp-gen4x2-pcie-phy @@ -58,7 +59,7 @@ properties: clocks: minItems: 5 - maxItems: 6 + maxItems: 10 clock-names: minItems: 5 @@ -68,20 +69,29 @@ properties: - const: ref - enum: [rchng, refgen] - const: pipe - - const: pipediv2 + - enum: [pipediv2, phy_b_aux] + - const: cfg_ahb_b + - const: rchng_b + - const: pipe_b + - const: pipediv2_b power-domains: - maxItems: 1 + minItems: 1 + items: + - description: PCIe PHY power domain. + - description: Additional PCIe PHY power domain (if present). resets: minItems: 1 - maxItems: 2 + maxItems: 4 reset-names: minItems: 1 items: - const: phy - const: phy_nocsr + - const: phy_b + - const: phy_b_nocsr vdda-phy-supply: true @@ -98,13 +108,29 @@ properties: - description: offset of PCIe 4-lane configuration register - description: offset of configuration bit for this PHY + qcom,link-mode: + description: + Configures the link mode of the PCIe PHY. Some PHYs support multiple + link modes, such as a single x8 link or two independent x4 links. The + link mode selection is performed by writing to a register in the TCSR + syscon, specified as a phandle to the syscon, the register offset, and + the link mode value. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle of TCSR syscon + - description: offset of link mode register + - description: link mode value + "#clock-cells": true clock-output-names: - maxItems: 1 + minItems: 1 + items: + - description: Name of the first pipe clock output. + - description: Name of the second pipe clock output (if present). - "#phy-cells": - const: 0 + "#phy-cells": true required: - compatible @@ -130,19 +156,40 @@ allOf: - qcom,sc8280xp-qmp-gen3x4-pcie-phy - qcom,x1e80100-qmp-gen4x4-pcie-phy - qcom,x1p42100-qmp-gen4x4-pcie-phy + - qcom,glymur-qmp-gen5x8-pcie-phy then: properties: reg: items: - description: port a - description: port b - required: - - qcom,4ln-config-sel else: properties: reg: maxItems: 1 + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-qmp-gen3x4-pcie-phy + - qcom,x1e80100-qmp-gen4x4-pcie-phy + - qcom,x1p42100-qmp-gen4x4-pcie-phy + then: + required: + - qcom,4ln-config-sel + + - if: + properties: + compatible: + contains: + enum: + - qcom,glymur-qmp-gen5x8-pcie-phy + then: + required: + - qcom,link-mode + - if: properties: compatible: @@ -198,8 +245,40 @@ allOf: properties: clocks: minItems: 6 + maxItems: 6 clock-names: minItems: 6 + maxItems: 6 + + - if: + properties: + compatible: + contains: + enum: + - qcom,glymur-qmp-gen5x8-pcie-phy + then: + properties: + clocks: + minItems: 10 + maxItems: 10 + clock-names: + items: + - const: aux + - const: cfg_ahb + - const: ref + - const: rchng + - const: pipe + - const: phy_b_aux + - const: cfg_ahb_b + - const: rchng_b + - const: pipe_b + - const: pipediv2_b + power-domains: + minItems: 2 + else: + properties: + power-domains: + maxItems: 1 - if: properties: @@ -223,11 +302,24 @@ allOf: reset-names: minItems: 2 else: - properties: - resets: - maxItems: 1 - reset-names: - maxItems: 1 + if: + properties: + compatible: + contains: + enum: + - qcom,glymur-qmp-gen5x8-pcie-phy + then: + properties: + resets: + minItems: 4 + reset-names: + minItems: 4 + else: + properties: + resets: + maxItems: 1 + reset-names: + maxItems: 1 - if: properties: @@ -237,6 +329,7 @@ allOf: - qcom,sm8450-qmp-gen4x2-pcie-phy - qcom,sm8550-qmp-gen4x2-pcie-phy - qcom,sm8650-qmp-gen4x2-pcie-phy + - qcom,glymur-qmp-gen5x8-pcie-phy then: properties: "#clock-cells": @@ -246,6 +339,25 @@ allOf: "#clock-cells": const: 0 + - if: + properties: + compatible: + contains: + enum: + - qcom,glymur-qmp-gen5x8-pcie-phy + then: + properties: + clock-output-names: + minItems: 2 + "#phy-cells": + const: 1 + else: + properties: + clock-output-names: + maxItems: 1 + "#phy-cells": + const: 0 + examples: - | #include -- 2.34.1