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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-302944ffdf0sm16288683eec.8.2026.05.18.22.47.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 22:47:25 -0700 (PDT) From: Qiang Yu Date: Mon, 18 May 2026 22:47:16 -0700 Subject: [PATCH RFC v4 5/9] phy: qcom: qmp-pcie: Refactor pipe clk register and parse_dt helpers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260518-link_mode_0519-v4-5-269cd73cc5d1@oss.qualcomm.com> References: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> In-Reply-To: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio Cc: Qiang Yu , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779169640; l=5256; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=MbaTZPbJ/JsKncMTk7duiSh2ZYiCvvSREcklhYtrLDc=; b=Dq3RCcs82o0H2virjARvXvlTSyqDuHN+lBQRphnHRjl/IthNFWB96EylAfdOP6gHzuQPubGCY 3RMr5wszk+1Ce83B2703ATv5W3RlvPKpcAXgRqGxLvicpvvGZAfXDtQ X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDA1MyBTYWx0ZWRfX+Sy8ZUZ4Vy9/ i0JrU219yBrpPdrNKC8gitYn6lgH6chNwW0cRyBjn+paTNbfZ2hbBQ+Np+XIqVmD5ptjJSqGBs2 CjD3eijCDL6sY1AC8DWl6jWRpGvu5C+5JtJhBW5ITCTYK8ECVDtvrNQ7m007124O5V46of2ZX3A tNF+oYsmUPtigENA75GdxlgJvdZM1HR1yz6q3stGg5E3SJQYodaCF7OayVkoMdzEg8Ljhlm6WdN 8SFrF3Pnk8bZ20A/msDRsF5kpkZXNve/E07ZVnysscvKKpqWfcsJv/ZMZ7VsDTGaSEryLWsg/6u CfrnfWBet5LtFHiGoE4kuyBD8Cymi6Q55pfmcpQdtDWJv2eINyzpVwDqJz7jmAYBEbYkmKtH5qh O2Uni/9wBLYZSk7WOGVfWP9EFiLAEV/I9D5eUeUDC8xCnebeLcH4nnKkHBbCTQSeEeIc0QDv9/R JAvepX8VDD1w+IOZMDA== X-Authority-Analysis: v=2.4 cv=A5Jc+aWG c=1 sm=1 tr=0 ts=6a0bf96f cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=2AX8zLxBezjo-DDFgScA:9 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-GUID: piqffNbghgTw1x-k8Fs-i_VgmeH9F83a X-Proofpoint-ORIG-GUID: piqffNbghgTw1x-k8Fs-i_VgmeH9F83a X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 spamscore=0 malwarescore=0 impostorscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190053 Some QMP PCIe PHY hardware blocks can be split into multiple sub-PHYs under a single DT node, each requiring its own pipe clock registration and DT resource mapping. The current helpers are tightly coupled to a single qmp_pcie instance, which prevents reuse across sub-PHY instances. Refactor __phy_pipe_clk_register() as a generic helper and reduce phy_pipe_clk_register() to a thin wrapper around it. Similarly, extract qmp_pcie_parse_dt_common() from qmp_pcie_parse_dt() to hold the register- mapping and pipe-clock setup that will be shared between sub-PHY instances, with pipe clock names parameterised per instance. This is a preparatory step before adding multi-PHY support. No functional change for existing platforms. Signed-off-by: Qiang Yu --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 76 ++++++++++++++++++-------------- 1 file changed, 44 insertions(+), 32 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 1dee4733d4f2..6332f15f78ca 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -5116,32 +5116,34 @@ static void phy_clk_release_provider(void *res) * clk | +-------+ | +-----+ * +---------------+ */ -static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np) +static int __phy_pipe_clk_register(struct device *dev, struct device_node *np, + int clk_name_index, struct clk_fixed_rate *fixed) { - struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; struct clk_init_data init = { }; int ret; - ret = of_property_read_string_index(np, "clock-output-names", 0, &init.name); + ret = of_property_read_string_index(np, "clock-output-names", clk_name_index, + &init.name); if (ret) { - dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); + dev_err(dev, "%pOFn: No clock-output-names\n", np); return ret; } init.ops = &clk_fixed_rate_ops; - /* - * Controllers using QMP PHY-s use 125MHz pipe clock interface - * unless other frequency is specified in the PHY config. - */ - if (qmp->cfg->pipe_clock_rate) - fixed->fixed_rate = qmp->cfg->pipe_clock_rate; - else + /* Default to 125MHz if caller did not pre-populate a rate. */ + if (!fixed->fixed_rate) fixed->fixed_rate = 125000000; fixed->hw.init = &init; - return devm_clk_hw_register(qmp->dev, &fixed->hw); + return devm_clk_hw_register(dev, &fixed->hw); +} + +static int phy_pipe_clk_register(struct qmp_pcie *qmp, struct device_node *np) +{ + qmp->pipe_clk_fixed.fixed_rate = qmp->cfg->pipe_clock_rate; + return __phy_pipe_clk_register(qmp->dev, np, 0, &qmp->pipe_clk_fixed); } /* @@ -5336,26 +5338,18 @@ static int qmp_pcie_get_4ln_config(struct qmp_pcie *qmp) return 0; } -static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) +static int qmp_pcie_parse_dt_common(struct qmp_pcie *qmp, void __iomem *base, + const char *pipe_clk_name, + const char *pipediv2_clk_name) { - struct platform_device *pdev = to_platform_device(qmp->dev); const struct qmp_phy_cfg *cfg = qmp->cfg; const struct qmp_pcie_offsets *offs = cfg->offsets; struct device *dev = qmp->dev; - void __iomem *base; int ret; if (!offs) return -EINVAL; - ret = qmp_pcie_get_4ln_config(qmp); - if (ret) - return ret; - - base = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(base)) - return PTR_ERR(base); - qmp->serdes = base + offs->serdes; qmp->pcs = base + offs->pcs; qmp->pcs_misc = base + offs->pcs_misc; @@ -5368,12 +5362,6 @@ static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) qmp->rx2 = base + offs->rx2; } - if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) { - qmp->port_b = devm_platform_ioremap_resource(pdev, 1); - if (IS_ERR(qmp->port_b)) - return PTR_ERR(qmp->port_b); - } - qmp->txz = base + offs->txz; qmp->rxz = base + offs->rxz; @@ -5381,17 +5369,41 @@ static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) qmp->ln_shrd = base + offs->ln_shrd; qmp->num_pipe_clks = 2; - qmp->pipe_clks[0].id = "pipe"; - qmp->pipe_clks[1].id = "pipediv2"; + qmp->pipe_clks[0].id = pipe_clk_name; + qmp->pipe_clks[1].id = pipediv2_clk_name; ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks); if (ret) return ret; - ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1); + return devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, + qmp->pipe_clks + 1); +} + +static int qmp_pcie_parse_dt(struct qmp_pcie *qmp) +{ + struct platform_device *pdev = to_platform_device(qmp->dev); + void __iomem *base; + int ret; + + ret = qmp_pcie_get_4ln_config(qmp); + if (ret) + return ret; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + ret = qmp_pcie_parse_dt_common(qmp, base, "pipe", "pipediv2"); if (ret) return ret; + if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) { + qmp->port_b = devm_platform_ioremap_resource(pdev, 1); + if (IS_ERR(qmp->port_b)) + return PTR_ERR(qmp->port_b); + } + return 0; } -- 2.34.1