From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 85C4E351C04 for ; Tue, 19 May 2026 05:47:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779169650; cv=none; b=rrp25MAQUV28NdktuyMQ9TP1YbLdo5fFX/UGJ7+5MkMKQ30+ae2HIoKxzB2eFWZ/B6fAv0joWeoR8tgOPJvLSJ8i4WhvKbBImMCpXE0pTuKkoDswS/Gq+3tkQuc803y0XzsDz2EiE7ra+BU0KjkjFE5IfpW56Vmu/SDICwGrwPQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779169650; c=relaxed/simple; bh=6l47wGwpcdS+i8z+96tTAR26f2jAl5baUJvJx2wGmVk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=aeylYTlZDBVPV/pIqFEU+P+ZNmcWRl4RLHODh/IKosDKnFGdSd6N4ubnm2dHmHCepd955DE1CfmFSEGvO5ICU/4GWfxPe71bZfc2EEgSwa373kQJfNoD0dVABMOaRwf6JRwVTjNY5IlTxynrW9CX6g51MJnguBcALatu5QFpX9k= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=Rt//YA81; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=DxVOzOpM; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="Rt//YA81"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="DxVOzOpM" Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 64J59ngA1251662 for ; Tue, 19 May 2026 05:47:28 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= ytn8hC+NMMnLU7PiLjFRS9m0hFgHKNq4bt/poY0T1tM=; b=Rt//YA81zM+mrLYi jU2KPCTCo3kLls912E+1OpCYhDqtb/zzUb77KReevcvVtq7JRi7xR2o3ZRTEZl0Z DkO+c3cFs0hPl/JNm+f61Y6OTYj1qxiRnTvhPN9RiI5AlaWaMuq6kMHno7FnXx5E jaT+V4jaYdiLdGWpambl9Hm1qbWk0VgsYee3RjEdfJj2Mu4fYzcdgNCJ9pfssbU7 CRiVhk33qWpNwW0RQ0QB6LWeniPuI5De+OLNTtnTSzslauBAbsPFaGqemYJnxRHA MqUln9ExXHVjvXHtnVv61N+1BiKgWg2BFarFWk5enb58IRi3T3Yv9o7MYaOe+S7D vf1trw== Received: from mail-dy1-f197.google.com (mail-dy1-f197.google.com [74.125.82.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4e82c0kj97-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Tue, 19 May 2026 05:47:27 +0000 (GMT) Received: by mail-dy1-f197.google.com with SMTP id 5a478bee46e88-2c16233ee11so4319752eec.1 for ; Mon, 18 May 2026 22:47:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1779169647; x=1779774447; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=ytn8hC+NMMnLU7PiLjFRS9m0hFgHKNq4bt/poY0T1tM=; b=DxVOzOpMqUM+F7Q9L52rCSf+QUhYlTfVMjVUV4ZGgw/EUt8pWtLk9UULVBGHi1+SZF cV4k0A5W64YPN2wmeorhKpx5Oxggq9PmdNgIxTKGPftVMiihRQlXKCs1MwFWD5wnEyKb xwh099QUvCbHtVrdXEnPzmLyS/vgiePR7rVnhEdQUhGQQkdBWne0eZg5jZuo78bXyV7Z VuGlW8s+dmJrMvLduTdMG7EBdfFhiJzufpLpzbzecJdXp0E+46nVkzSAqhFIEo0N8PZI UEaMFiHWfZ3psEj5xJgen1XY5Yx8RSh9gqVzoOVv9vOczZGpIynetxb14y4+c9Exy4hH V4QQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1779169647; x=1779774447; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=ytn8hC+NMMnLU7PiLjFRS9m0hFgHKNq4bt/poY0T1tM=; b=DvRd/GUOqw34VYHpgWgWdoNeiHq+TiO646QwmFknTzPtJO/l89M0mvPYQAeeTguymv tKeVE4ByGvAPH6Sa88YefU+q13YnOnq2V3LWBhSmmpkg+aeNCUoXzVz7tWFLKTU3hrT5 VddtkVrX6Hqnlt5GoMM00G8AnIMelbdy7v/zyZliF8J2TJZbPd/QRs990S3+ggCGQFWG VUxIVi9kg2dq0KW6MhaqHhx4YZdRKxuRLA3fbwYMqUk/qdD9PmlnmTQWoBCiOP/77Ztq sj15Mc658+DKlFvGHXVaB+YKfMqpRbwu7xYSViVT+NjvRwwxeHVDNatCN+D2WIAA+grf BynQ== X-Forwarded-Encrypted: i=1; AFNElJ+aFKPjYP1P5NFdMfPdn2peOjIvFuXIfz6nzkZvD74ncHrAisGub4/PMxY46jpMGbhal0WnzDwkKG+ab0U=@vger.kernel.org X-Gm-Message-State: AOJu0Yx6rvK/EulrHavZpgDmxAVRJXhWuJXqKn8eN5j/1g0zNZmX9/36 isAEOW2VBxCdpT1zNJsYhymUa26wVc4OJny2bZy91qb8V++CJBsRtgaFBYIiy1jcGpRyb00GCsd qqWpX3B6k3vhsHeRxfvDWZKScjSVFow4QD3I1o9o8BgV+92a/pfCLydu3y6GcVBnKhb8= X-Gm-Gg: Acq92OFRxSedtDefm2B1Z59NcQMoeBQJLdasEBd9RqdEOIE5xXCGp8EdKxT6t68H5Ek T0iyaN4B/e0KVVuETI9n2R7Wb0uHWx+Rbjx625wECBYAxPc9WfIlSOdcCTfb+vajpgmx6HPhi3f 8OduD/5sT8llrAK36qHq8RuGsYF1vy+3d0mJVhynpZ+yGKz/+SLEGxz8KD4l86uD1HfH3X1arEj o9diM1L1lhpjbIFsSDCQZ1NIR1Ap2mIUfD+Qsl31ZzBtGE1G7X3UL0rlj/K05y1vMvlnT2obWoy P/mfyFhpkje7hATpdwK265rZ0DwEiZxWM1VxW/nXib76Pd/Y1Iizg3xy1i5zzuoM5z+1dOGq/Ki 3gQkgeP02nmQUkM5yO6xLbihnd8xga3nQbAHEE4SrENYY2HiXWVbphktn5krbSz4p7xI+ X-Received: by 2002:a05:7300:e7a2:b0:2ea:b85c:153d with SMTP id 5a478bee46e88-303986948camr7474789eec.27.1779169647145; Mon, 18 May 2026 22:47:27 -0700 (PDT) X-Received: by 2002:a05:7300:e7a2:b0:2ea:b85c:153d with SMTP id 5a478bee46e88-303986948camr7474764eec.27.1779169646587; Mon, 18 May 2026 22:47:26 -0700 (PDT) Received: from hu-qianyu-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-302944ffdf0sm16288683eec.8.2026.05.18.22.47.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 22:47:26 -0700 (PDT) From: Qiang Yu Date: Mon, 18 May 2026 22:47:17 -0700 Subject: [PATCH RFC v4 6/9] phy: qcom: qmp-pcie: Add clock and reset lists for secondary PHY selector Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260518-link_mode_0519-v4-6-269cd73cc5d1@oss.qualcomm.com> References: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> In-Reply-To: <20260518-link_mode_0519-v4-0-269cd73cc5d1@oss.qualcomm.com> To: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Bjorn Andersson , Konrad Dybcio Cc: Qiang Yu , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1779169640; l=4489; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=6l47wGwpcdS+i8z+96tTAR26f2jAl5baUJvJx2wGmVk=; b=tI+M9vo4rfmkJHBISreYDBHdrX+sGAXFh9++C+YnE/xQL8MIXjFsLioMqHH2TrO7750kRU3Nu H8j3v/bQPN/CNxaRDMTldfJKYU89Zz4ECL8idv4ADT7LCrZmQHTaRFf X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE5MDA1MyBTYWx0ZWRfX+XSnYILJc3yT kysXvuwv2cK0jdeXquCyhP1b6g4fV8eoDNWZYQMqrCLNOdUhKCBfPoZbBQ69AHU0R8R1PsO4Lz3 W1pGWk44uLQu8w3fbpNno4T9OrsiqywWV6xStLZdbQkU0nOOC/nQfmdThISVJKl8iEsk/fiEZFu pphEQBzdZ9AuqkgpKdXcSvtfhSUl40DpklCKMhUgSXF5kZg1RHdmGHoNPGFW96hU1D3d/VKFSTQ fWtmKgpY6z6GjMJI+SSzuKE7Y6lGZJ+G6WU/gEVtPlNeXR1grBGmR56Vs8IuiDx2VvYMajAFORM 8C1XpcwoUQ+GqwYqGW8BqqrLL26PqCU9YDGFOOLq6vGB4YqX+yAqFUUf1ggOB18aNIzBOKYdTWs ZJLyAQDRpaH/XXwnIH10GxgzHGfCPtRIMApgfUw7mCXfHfVBwAzQofQuujznfkdYr91XTdkDv3i sYh1c3lPe5fAowth1pg== X-Authority-Analysis: v=2.4 cv=A5Jc+aWG c=1 sm=1 tr=0 ts=6a0bf96f cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=ee-eAjM40MESQSg1XYEA:9 a=QEXdDO2ut3YA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-GUID: F95QDSV4qq7b8lzotIt-gXZ_Jz4uLNEH X-Proofpoint-ORIG-GUID: F95QDSV4qq7b8lzotIt-gXZ_Jz4uLNEH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-19_02,2026-05-18_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 spamscore=0 malwarescore=0 impostorscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605130000 definitions=main-2605190053 PHY instances sharing a single DT node each need their own clocks and resets. The current driver uses a single hardcoded clock list with no way to select per-instance resources. Add the infrastructure needed before wiring up multi-PHY probe. qmp_pciephy_secondary_clk_l[] and qmp_pcie_get_clk_list(id) are added to select the appropriate clock list by PHY selector index. qmp_pcie_num_clks() replaces the hard-coded ARRAY_SIZE(qmp_pciephy_clk_l) in qmp_pcie_init(), qmp_pcie_exit(), and qmp_pcie_clk_init(). struct qmp_pcie::phy is replaced with an id field so each instance can identify its index within a multi-PHY provider. Signed-off-by: Qiang Yu --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 49 ++++++++++++++++++++++++++------ 1 file changed, 40 insertions(+), 9 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 6332f15f78ca..b100302be12a 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -3335,7 +3335,7 @@ struct qmp_pcie { struct reset_control_bulk_data *nocsr_reset; struct regulator_bulk_data *vregs; - struct phy *phy; + u32 id; int mode; struct clk_fixed_rate pipe_clk_fixed; @@ -3379,6 +3379,24 @@ static const char * const qmp_pciephy_clk_l[] = { "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", }; +static const char * const qmp_pciephy_secondary_clk_l[] = { + "ref", "phy_b_aux", "cfg_ahb_b", "rchng_b", +}; + +static int qmp_pcie_get_clk_list(u32 id, const char * const **clk_list) +{ + switch (id) { + case QMP_PHY_SELECTOR_0: + *clk_list = qmp_pciephy_clk_l; + return ARRAY_SIZE(qmp_pciephy_clk_l); + case QMP_PHY_SELECTOR_1: + *clk_list = qmp_pciephy_secondary_clk_l; + return ARRAY_SIZE(qmp_pciephy_secondary_clk_l); + default: + return -EINVAL; + } +} + /* list of regulators */ static const char * const qmp_phy_vreg_l[] = { "vdda-phy", "vdda-pll", @@ -4781,6 +4799,13 @@ static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_c qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num); } +static int qmp_pcie_num_clks(const struct qmp_pcie *qmp) +{ + const char * const *clk_list; + + return qmp_pcie_get_clk_list(qmp->id, &clk_list); +} + static int qmp_pcie_init(struct phy *phy) { struct qmp_pcie *qmp = phy_get_drvdata(phy); @@ -4840,7 +4865,7 @@ static int qmp_pcie_init(struct phy *phy) } } - ret = clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); + ret = clk_bulk_prepare_enable(qmp_pcie_num_clks(qmp), qmp->clks); if (ret) goto err_assert_reset; @@ -4865,7 +4890,7 @@ static int qmp_pcie_exit(struct phy *phy) else reset_control_bulk_assert(cfg->num_resets, qmp->resets); - clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); + clk_bulk_disable_unprepare(qmp_pcie_num_clks(qmp), qmp->clks); regulator_bulk_disable(cfg->num_vregs, qmp->vregs); @@ -5079,16 +5104,21 @@ static int qmp_pcie_reset_init(struct qmp_pcie *qmp) static int qmp_pcie_clk_init(struct qmp_pcie *qmp) { + const char * const *clk_list; struct device *dev = qmp->dev; - int num = ARRAY_SIZE(qmp_pciephy_clk_l); + int num; int i; + num = qmp_pcie_get_clk_list(qmp->id, &clk_list); + if (num < 0) + return num; + qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); if (!qmp->clks) return -ENOMEM; for (i = 0; i < num; i++) - qmp->clks[i].id = qmp_pciephy_clk_l[i]; + qmp->clks[i].id = clk_list[i]; return devm_clk_bulk_get_optional(dev, num, qmp->clks); } @@ -5414,6 +5444,7 @@ static int qmp_pcie_probe(struct platform_device *pdev) struct phy_provider *phy_provider; struct device_node *np; struct qmp_pcie *qmp; + struct phy *phy; int ret; qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); @@ -5468,14 +5499,14 @@ static int qmp_pcie_probe(struct platform_device *pdev) qmp->mode = PHY_MODE_PCIE_RC; - qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops); - if (IS_ERR(qmp->phy)) { - ret = PTR_ERR(qmp->phy); + phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops); + if (IS_ERR(phy)) { + ret = PTR_ERR(phy); dev_err(dev, "failed to create PHY: %d\n", ret); goto err_node_put; } - phy_set_drvdata(qmp->phy, qmp); + phy_set_drvdata(phy, qmp); of_node_put(np); -- 2.34.1