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Both topologies are served by the same DT node since they share the same hardware block and TCSR mode register. Per-topology reset and clock lists are introduced alongside the PHY configs to reflect the different resource ownership in each mode. The per-mode PHY configurations and match data are then added to wire the two topologies into the link-mode infrastructure introduced in the previous patch. Signed-off-by: Qiang Yu --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 80 +++++++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index d78d57fb64d6..d4aeb3e00955 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -3399,7 +3399,7 @@ static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) /* list of clocks required by phy */ static const char * const qmp_pciephy_clk_l[] = { - "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", + "aux", "cfg_ahb", "ref", "refgen", "rchng", "phy_aux", "phy_b_aux", }; static const char * const qmp_pciephy_secondary_clk_l[] = { @@ -4746,6 +4746,81 @@ static const struct qmp_phy_cfg glymur_qmp_gen4x2_pciephy_cfg = { .phy_status = PHYSTATUS_4_20, }; +static const char * const qmp_pciephy_secondary_reset_l[] = { + "phy_b", +}; + +static const char * const qmp_pciephy_secondary_nocsr_reset_l[] = { + "phy_b_nocsr", +}; + +static const char * const glymur_pciephy_reset_l[] = { + "phy", "phy_b" +}; + +static const char * const glymur_pciephy_nocsr_reset_l[] = { + "phy_nocsr", "phy_b_nocsr", +}; + +static const struct qmp_phy_cfg glymur_qmp_gen5x4_secondary_pciephy_cfg = { + .lanes = 4, + + .offsets = &qmp_pcie_offsets_v8_50, + + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .reset_list = qmp_pciephy_secondary_reset_l, + .num_resets = ARRAY_SIZE(qmp_pciephy_secondary_reset_l), + .nocsr_reset_list = qmp_pciephy_secondary_nocsr_reset_l, + .num_nocsr_resets = ARRAY_SIZE(qmp_pciephy_secondary_nocsr_reset_l), + + .regs = pciephy_v8_50_regs_layout, + + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS_4_20, +}; + +static const struct qmp_phy_cfg glymur_qmp_gen5x8_pciephy_cfg = { + .lanes = 8, + + .offsets = &qmp_pcie_offsets_v8_50, + + .reset_list = glymur_pciephy_reset_l, + .num_resets = ARRAY_SIZE(glymur_pciephy_reset_l), + .nocsr_reset_list = glymur_pciephy_nocsr_reset_l, + .num_nocsr_resets = ARRAY_SIZE(glymur_pciephy_nocsr_reset_l), + .vreg_list = qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + + .regs = pciephy_v8_50_regs_layout, + + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, + .phy_status = PHYSTATUS_4_20, +}; + +static const struct qmp_pcie_link_mode_cfg glymur_qmp_gen5x8_mode_cfgs[] = { + [QMP_PCIE_GLYMUR_MODE_X8] = { + /* x8 */ + .cfgs = { + [QMP_PHY_SELECTOR_0] = &glymur_qmp_gen5x8_pciephy_cfg, + }, + .num_phys = 1, + }, + [QMP_PCIE_GLYMUR_MODE_X4X4] = { + /* x4 + x4 */ + .cfgs = { + [QMP_PHY_SELECTOR_0] = &glymur_qmp_gen5x4_pciephy_cfg, + [QMP_PHY_SELECTOR_1] = &glymur_qmp_gen5x4_secondary_pciephy_cfg, + }, + .num_phys = 2, + }, +}; + +static const struct qmp_pcie_match_data glymur_qmp_gen5x8_match_data = { + .mode_cfgs = glymur_qmp_gen5x8_mode_cfgs, + .num_modes = ARRAY_SIZE(glymur_qmp_gen5x8_mode_cfgs), +}; + static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls) { const struct qmp_phy_cfg *cfg = qmp->cfg; @@ -5797,6 +5872,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = { }, { .compatible = "qcom,glymur-qmp-gen5x4-pcie-phy", .data = &glymur_qmp_gen5x4_pciephy_cfg, + }, { + .compatible = "qcom,glymur-qmp-gen5x8-pcie-phy", + .data = &glymur_qmp_gen5x8_match_data, }, { .compatible = "qcom,ipq6018-qmp-pcie-phy", .data = &ipq6018_pciephy_cfg, -- 2.34.1