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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83f8b9c2ea5sm2641252b3a.13.2026.05.18.22.51.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 22:51:57 -0700 (PDT) From: Joey Lu To: zhengxingda@iscas.ac.cn, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH v2 0/4] drm/verisilicon: add Nuvoton MA35D1 DCU Lite support Date: Tue, 19 May 2026 13:51:05 +0800 Message-ID: <20260519055114.1886525-1-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit This series adds support for the Verisilicon DCU Lite display controller as integrated in the Nuvoton MA35D1 SoC. The Verisilicon DC driver and its DT binding were originally written by Icenowy Zheng for the T-Head TH1520 SoC, which carries a DC8200 IP block. The present series builds on that foundation with gratitude to Icenowy for the original work. The DCU Lite is a different variant in the DC IP family. While the two IPs share a broadly similar register layout, a number of differences prevent the existing driver from working on the MA35D1 without modification: - No CONFIG_EX commit path: the DC8200 staging registers (FB_CONFIG_EX, FB_TOP_LEFT, FB_BOTTOM_RIGHT, FB_BLEND_CONFIG, PANEL_CONFIG_EX) are absent. The DCU Lite uses enable (bit 0) and reset (bit 4) bits in FB_CONFIG for direct framebuffer updates, and requires a per-frame VALID bit toggle (FB_CONFIG bit 3) to latch configuration changes. - No PANEL_START register: panel output begins when PANEL_CONFIG.RUNNING is set; the DC8200 multi-display sync start register at 0x1CCC does not exist. - Different IRQ registers: DISP_IRQ_STA at 0x147C / DISP_IRQ_EN at 0x1480, versus the DC8200's TOP_IRQ_ACK at 0x0010 / TOP_IRQ_EN at 0x0014. - Simpler clock topology: two clocks ("core" bus gate and "pix0" pixel divider); no axi or ahb clocks required. - Single display output: no per-output indexing beyond index 0 is needed. - Hardware-discoverable identity: the DCU Lite exposes chip identity registers whose model field reads 0x0 (revision 0x5560, customer_id 0x305), allowing the existing vs_fill_chip_identity() path to identify the variant purely through register reads. No separate OF compatible string is introduced. Patch 1 generalises the verisilicon,dc DT binding to accommodate variants with flexible clock/reset counts and a single output, using allOf/if-then-else to keep per-variant constraints in-schema. Patches 2-4 introduce the driver changes in three logical steps: register-level constants and the DCU Lite chip identity table entry; the vs_dc_funcs hardware ops table with DC8200 ops extracted into vs_dc8200.c; and finally the DCU Lite ops in vs_dcu_lite.c with the necessary Kconfig and clock-optionality changes. All patches have been tested on Nuvoton MA35D1 hardware. Changes from v1: - Corrected "DC8000" to "DC8200" throughout (the existing supported IP is DC8200, not DC8000). - Dropped the separate nuvoton,ma35d1-dcu.yaml; variant constraints are now expressed inline in verisilicon,dc.yaml via allOf/if-then-else. The MA35D1 uses the generic "verisilicon,dc" compatible string. - Replaced the vs_dc_info platform-data flags approach with a vs_dc_funcs hardware ops table, giving cleaner per-variant dispatch without scattering if/else branches across multiple files. - DCU Lite variant is identified through hardware registers rather than the OF match table. - Series split from 2 patches to 4 for clearer logical progression. - Renamed plane ops in vs_dc_funcs: plane_enable/disable to plane_enable_ex/disable_ex, plane_update_ext to plane_update_ex. Joey Lu (4): dt-bindings: display: verisilicon,dc: generalize for single-output variants drm/verisilicon: add model ID constants and DCU Lite chip identity drm/verisilicon: introduce per-variant hardware ops table drm/verisilicon: add Nuvoton MA35D1 DCU Lite display controller support .../bindings/display/verisilicon,dc.yaml | 135 ++++++++++++++---- drivers/gpu/drm/verisilicon/Kconfig | 2 +- drivers/gpu/drm/verisilicon/Makefile | 2 +- drivers/gpu/drm/verisilicon/vs_bridge.c | 20 +-- drivers/gpu/drm/verisilicon/vs_crtc.c | 38 ++++- drivers/gpu/drm/verisilicon/vs_crtc_regs.h | 1 + drivers/gpu/drm/verisilicon/vs_dc.c | 13 +- drivers/gpu/drm/verisilicon/vs_dc.h | 33 +++++ drivers/gpu/drm/verisilicon/vs_dc8200.c | 107 ++++++++++++++ drivers/gpu/drm/verisilicon/vs_dcu_lite.c | 78 ++++++++++ drivers/gpu/drm/verisilicon/vs_hwdb.c | 16 ++- drivers/gpu/drm/verisilicon/vs_hwdb.h | 3 + .../gpu/drm/verisilicon/vs_primary_plane.c | 32 +---- .../drm/verisilicon/vs_primary_plane_regs.h | 3 + 14 files changed, 398 insertions(+), 85 deletions(-) create mode 100644 drivers/gpu/drm/verisilicon/vs_dc8200.c create mode 100644 drivers/gpu/drm/verisilicon/vs_dcu_lite.c -- 2.43.0