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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83f8b9c2ea5sm2641252b3a.13.2026.05.18.22.51.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 18 May 2026 22:52:01 -0700 (PDT) From: Joey Lu To: zhengxingda@iscas.ac.cn, maarten.lankhorst@linux.intel.com, mripard@kernel.org, tzimmermann@suse.de, airlied@gmail.com, simona@ffwll.ch, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: ychuang3@nuvoton.com, schung@nuvoton.com, yclu4@nuvoton.com, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Joey Lu Subject: [PATCH v2 1/4] dt-bindings: display: verisilicon,dc: generalize for single-output variants Date: Tue, 19 May 2026 13:51:06 +0800 Message-ID: <20260519055114.1886525-2-a0987203069@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260519055114.1886525-1-a0987203069@gmail.com> References: <20260519055114.1886525-1-a0987203069@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The existing schema assumes a fixed clock/reset topology and dual-output port structure matching the DC8200 IP block. This prevents reuse for single-output variants such as the Verisilicon DCU Lite used in the Nuvoton MA35D1 SoC. Rework the schema so that variant-specific constraints are expressed via allOf/if-then-else: - The thead,th1520-dc8200 compatible keeps its existing five-clock, three-reset, dual-port requirements. - A standalone verisilicon,dc compatible covers IPs whose identity is discovered entirely through hardware registers; these have flexible clock and reset counts, a single 'port' property, and no 'ports' requirement. Changes to the base schema: - Replace the fixed clock/reset items lists with minItems/maxItems ranges; variant sub-schemas tighten the constraints via if-then-else. - Add a 'port' property (graph.yaml single-port alias) alongside the existing 'ports', for single-output variants. - Drop the unconditional 'ports' requirement; each if-branch enforces its own port topology. - Tighten additionalProperties to unevaluatedProperties to allow per-variant schemas to add their own constraints cleanly. - Fix a stray space in the port@0 description. - Add a DT example for the generic verisilicon,dc compatible (Nuvoton MA35D1 DCU Lite). Signed-off-by: Joey Lu --- .../bindings/display/verisilicon,dc.yaml | 135 ++++++++++++++---- 1 file changed, 108 insertions(+), 27 deletions(-) diff --git a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml index 9dc35ab973f2..3a814c2e083e 100644 --- a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml +++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml @@ -14,10 +14,12 @@ properties: pattern: "^display@[0-9a-f]+$" compatible: - items: - - enum: - - thead,th1520-dc8200 - - const: verisilicon,dc # DC IPs have discoverable ID/revision registers + oneOf: + - items: + - enum: + - thead,th1520-dc8200 + - const: verisilicon,dc + - const: verisilicon,dc # DC IPs have discoverable ID/revision registers reg: maxItems: 1 @@ -26,32 +28,24 @@ properties: maxItems: 1 clocks: - items: - - description: DC Core clock - - description: DMA AXI bus clock - - description: Configuration AHB bus clock - - description: Pixel clock of output 0 - - description: Pixel clock of output 1 + minItems: 2 + maxItems: 5 clock-names: - items: - - const: core - - const: axi - - const: ahb - - const: pix0 - - const: pix1 + minItems: 2 + maxItems: 5 resets: - items: - - description: DC Core reset - - description: DMA AXI bus reset - - description: Configuration AHB bus reset + minItems: 1 + maxItems: 3 reset-names: - items: - - const: core - - const: axi - - const: ahb + minItems: 1 + maxItems: 3 + + port: + $ref: /schemas/graph.yaml#/properties/port + description: Single video output port for single-output variants. ports: $ref: /schemas/graph.yaml#/properties/ports @@ -59,7 +53,7 @@ properties: properties: port@0: $ref: /schemas/graph.yaml#/properties/port - description: The first output channel , endpoint 0 should be + description: The first output channel, endpoint 0 should be used for DPI format output and endpoint 1 should be used for DP format output. @@ -75,9 +69,75 @@ required: - interrupts - clocks - clock-names - - ports -additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + const: thead,th1520-dc8200 + then: + properties: + clocks: + items: + - description: DC Core clock + - description: DMA AXI bus clock + - description: Configuration AHB bus clock + - description: Pixel clock of output 0 + - description: Pixel clock of output 1 + + clock-names: + items: + - const: core + - const: axi + - const: ahb + - const: pix0 + - const: pix1 + + resets: + items: + - description: DC Core reset + - description: DMA AXI bus reset + - description: Configuration AHB bus reset + + reset-names: + items: + - const: core + - const: axi + - const: ahb + + required: + - ports + + else: + properties: + clocks: + items: + - description: Bus clock that gates register access + - description: Pixel clock divider for display timing + + clock-names: + items: + - const: core + - const: pix0 + + resets: + maxItems: 1 + description: + Reset line for the display controller. + + reset-names: + items: + - const: core + + required: + - port + + not: + required: + - ports + +unevaluatedProperties: false examples: - | @@ -120,3 +180,24 @@ examples: }; }; }; + + - | + #include + #include + #include + + display@40260000 { + compatible = "verisilicon,dc"; + reg = <0x40260000 0x20000>; + interrupts = ; + clocks = <&clk DCU_GATE>, <&clk DCUP_DIV>; + clock-names = "core", "pix0"; + resets = <&sys MA35D1_RESET_DISP>; + reset-names = "core"; + + port { + dpi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; -- 2.43.0